FPGA & adaptive SoC databook ยท online editionRev. 2026.10

Altera Agilex 5 D-Series FPGAs

The Altera Agilex 5 D-Series family has 5 devices, built on the Intel 7 process, ranging from 175K ALMs to 548K ALMs and from 1,472 to 4,968 variable-precision DSP blocks. It uses adaptive logic modules (ALMs). Transceivers: XCVR, up to 28 Gb/s.

DeviceLUT4-eq.Vendor logicDSPBlock RAMMax I/OTransceiversPCIe
A5D 051349K 175K ALMs515K LE1,47250.1 Mb44424 XCVR 28 Gb/sGen4
A5D 064437K 218K ALMs644K LE1,84062.6 Mb44432 XCVR 28 Gb/sGen4
A5D 110728K 364K ALMs1074K LE3,312104.3 Mb61624 XCVR 28 Gb/sGen4
A5D 130877K 438K ALMs1293K LE3,864125.2 Mb88848 XCVR 28 Gb/sGen4
A5D 1601096K 548K ALMs1617K LE4,968156.4 Mb88848 XCVR 28 Gb/sGen4

Source: Altera Agilex 5 FPGAs and SoCs D-Series Product Table, 2026.08.07.