A5D 130
AlteraAgilex 5 D-SeriesThe A5D 130 is an Agilex 5 D-Series FPGA from Altera, built on the Intel 7 process. It provides 438,400 adaptive logic modules (ALMs) (1,293,280 logic elements (LEs)), about 876,800 LUT4 equivalents, 1,753,600 flip-flops, 125.2 Mb of block RAM and 3,864 variable-precision DSP blocks. Versions with the optional hard processor system include four Arm Cortex-A76 + Cortex-A55 cores. The programmable logic offers up to 888 user I/O pins and 48 XCVR transceivers at up to 28 Gb/s, with hard PCI Express Gen4 x8 blocks. Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Agilex 5 D-Series |
| Series | Agilex |
| Process | Intel 7 |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 876,800 |
| Adaptive logic modules (ALMs) | 438,400 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 1,293,280 |
| Flip-flops | 1,753,600 |
| Distributed RAM | 13,701 Kb |
| Block RAM | 125.2 Mb (6408 × 20 Kb) |
| DSP (variable-precision DSP block) | 3,864 |
| Max. user I/O | 888 |
|---|---|
| XCVR transceivers | 48 × 28 Gb/s |
| PCI Express (PL) | 12× Gen4 x4, 6× Gen4 x8 |
| Analog / monitor | None |
| Hard processor | 4× Arm Cortex-A76 + Cortex-A55 (optional, HPS variants) |
| Design tool | Altera Quartus Prime |
Alternatives to the A5D 130
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| AGF 012Altera Agilex 7 F-Series | 799K 400K ALMs | 1179K LE | 3,743 | 115 Mb | 768 | 32 XCVR 58 Gb/s | — |
| AGF 014Altera Agilex 7 F-Series | 974K 487K ALMs | 1437K LE | 4,510 | 139 Mb | 768 | 32 XCVR 58 Gb/s | — |
| SX 1100Altera Stratix 10 GX/SX | 899K 449K ALMs | 1325K LE | 2,592 | 107 Mb | 688 | 48 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 1650Altera Stratix 10 GX/SX | 1101K 551K ALMs | 1624K LE | 3,145 | 114 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| SX 2100Altera Stratix 10 GX/SX | 1359K 680K ALMs | 2005K LE | 3,744 | 127 Mb | 704 | 96 XCVR/XCVR 28.3 Gb/s | Gen3 |
| Ti1600Efinix Titanium | ≈1578K 1578K LEs | 1578K LE | 3,050 | 93.6 Mb | 480 | 40 SERDES 25.8 Gb/s | Gen4 |
Compare side by side: A5D 130 vs AGF 012, A5D 130 vs AGF 014, A5D 130 vs SX 1100, A5D 130 vs SX 1650, A5D 130 vs SX 2100.
A5D 130 quick facts
How many LUTs does the A5D 130 have?
The A5D 130 has 438,400 adaptive logic modules (ALMs), about 876,800 LUT4 equivalents (1,293,280 logic elements (les) as published by Altera).
How many DSP blocks does the A5D 130 have?
The A5D 130 has 3,864 variable-precision DSP blocks and 125.2 Mb of block RAM.
Does the A5D 130 have transceivers?
Yes, 48 XCVR transceivers at up to 28 Gb/s.
Does the A5D 130 have a processor?
Yes. Variants with the optional hard processor system include a 4× Arm Cortex-A76 + Cortex-A55 processor.
What are the alternatives to the A5D 130?
Devices of similar size in other families include AGF 012 (Altera Agilex 7 F-Series), AGF 014 (Altera Agilex 7 F-Series), SX 1100 (Altera Stratix 10 GX/SX).
Which software is used to design with the A5D 130?
Designs for the A5D 130 are built with Altera Quartus Prime.
Other Agilex 5 D-Series devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| A5D 051 | 349K 175K ALMs | 515K LE | 1,472 | 50.1 Mb | 444 | 24 XCVR 28 Gb/s | Gen4 |
| A5D 064 | 437K 218K ALMs | 644K LE | 1,840 | 62.6 Mb | 444 | 32 XCVR 28 Gb/s | Gen4 |
| A5D 110 | 728K 364K ALMs | 1074K LE | 3,312 | 104.3 Mb | 616 | 24 XCVR 28 Gb/s | Gen4 |
| A5D 130 | 877K 438K ALMs | 1293K LE | 3,864 | 125.2 Mb | 888 | 48 XCVR 28 Gb/s | Gen4 |
| A5D 160 | 1096K 548K ALMs | 1617K LE | 4,968 | 156.4 Mb | 888 | 48 XCVR 28 Gb/s | Gen4 |
Source: Altera Agilex 5 FPGAs and SoCs D-Series Product Table, 2026.08.07. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.