The Gate Array API

Read the specifications of 441 FPGAs and adaptive SoCs as JSON. The API is free, needs no key or registration and can be called from any website (CORS is open).

Quick start

Take the address of any device page and add /api in front of the path. The page of the AMD XC7A35T is https://thegatearray.com/amd/artix-7/xc7a35t/, so its data is at:

https://thegatearray.com/api/amd/artix-7/xc7a35t/

The same rule works for vendor and family pages. Paths use lowercase identifiers with hyphens, exactly as in the page addresses; use the FPGA finder to find a device and copy its path, or walk the API from /api/ down.

Endpoints

/api/e.g. /api/	List of vendors, with the number of devices
/api/<vendor>/e.g. /api/amd/	Families of a vendor
/api/<vendor>/<family>/e.g. /api/amd/artix-7/	Family details and a summary of each device, sorted by size
/api/<vendor>/<family>/<part>/e.g. /api/amd/artix-7/xc7a35t/	All the data of one device
/api/<vendor>/<family>/<part>/packages/e.g. /api/amd/artix-7/xc7a35t/packages/	Packages of one device: name, body size, area, ball pitch, user I/O and transceivers in each package

Every response includes url (the web page) and api (its own address), and lists link to the next level with their api field, so a client can follow the links instead of building paths.

Examples

curl

curl -s https://thegatearray.com/api/amd/artix-7/xc7a35t/

# Only the LUT4 equivalents, with jq
curl -s https://thegatearray.com/api/amd/artix-7/xc7a35t/ | jq .derived.lut4_equivalent

Python

import json, urllib.request

url = "https://thegatearray.com/api/amd/artix-7/xc7a35t/"
with urllib.request.urlopen(url) as r:
    dev = json.load(r)

print(dev["part"], dev["specs"]["luts"], dev["family_info"]["lut_type"])
for pkg in dev["specs"]["packages"]:
    print(pkg["name"], pkg["io"], "I/O")

JavaScript

const r = await fetch("https://thegatearray.com/api/amd/artix-7/xc7a35t/");
const dev = await r.json();

console.log(dev.part, dev.derived.lut4_equivalent, "LUT4-eq.");
console.log(dev.specs.transceivers.map(t => `${t.count} × ${t.type}`).join(", "));

Device response

A device has three groups of data. specs holds the values as extracted from the vendor's selection guide; fields that do not apply to a device are left out or set to null, and some devices have extra fields such as hbm_gb, ai_engines, eth100g or memory_controller. derived holds the values computed by The Gate Array. family_info describes the family and the source document.

specs.logic_cells	Vendor logic figure (logic cells, system logic cells or logic elements; unit in family_info.logic_unit)
specs.luts	Physical LUTs (or ALMs for Altera); type in family_info.lut_type. null when the vendor does not publish it
specs.ffs	Flip-flops
specs.dist_ram_kb	Distributed (LUT) RAM, Kb
specs.bram_blocks / bram_block_kb / bram_mb	Block RAM: number of blocks, size of each block (Kb) and total (Mb)
specs.uram_blocks / uram_mb	Large RAM (UltraRAM or equivalent; type in family_info.large_ram_type)
specs.dsp	DSP blocks or hard multipliers; type in family_info.dsp_type
specs.max_io	Maximum user I/O in any package
specs.transceivers[]	One entry per transceiver type: type, count and gbps (null if not published)
specs.pcie[]	Hard PCI Express blocks: gen, lanes and blocks when published
specs.cpu	Hard processor or null: arch, cores, mhz, optional, and rt, gpu, ps_io, ps_gtr for SoCs
specs.adc	On-chip ADC or analog monitor (e.g. "XADC"), or null
specs.grades	Temperature grade (C, E, I, Q, A, M) → list of speed grades
specs.packages[]	name, size_mm, pitch_mm, user io and transceivers for each package
derived.lut4_equivalent	Logic in LUT4 equivalents: LUT4 × 1, LUT6 × 1.6, ALM × 2
derived.lut4_equivalent_from_les	true when the vendor publishes no LUT count and the value comes from its logic elements
derived.transceiver_count / max_transceiver_gbps / max_pcie_gen	Totals computed from specs, handy for filtering
family_info.source	Document, version and URL the data was extracted from

Full response for the XC7A35T:

{
 "part": "XC7A35T",
 "id": "xc7a35t",
 "vendor": "AMD",
 "family": "Artix-7",
 "url": "https://thegatearray.com/amd/artix-7/xc7a35t/",
 "api": "https://thegatearray.com/api/amd/artix-7/xc7a35t/",
 "packages_api": "https://thegatearray.com/api/amd/artix-7/xc7a35t/packages/",
 "specs": {
  "logic_cells": 33280,
  "luts": 20800,
  "ffs": 41600,
  "dist_ram_kb": 400,
  "bram_blocks": 50,
  "bram_mb": 1.8,
  "uram_blocks": 0,
  "uram_mb": 0,
  "dsp": 90,
  "clock_mgmt": 5,
  "max_io": 250,
  "max_diff_pairs": 120,
  "transceivers": [
   {
    "type": "GTP",
    "count": 4,
    "gbps": 6.6
   }
  ],
  "pcie": [
   {
    "gen": 2,
    "blocks": 1
   }
  ],
  "adc": "XADC",
  "cpu": null,
  "grades": {
   "C": [
    "-1",
    "-2"
   ],
   "E": [
    "-2L",
    "-3"
   ],
   "I": [
    "-1",
    "-2",
    "-1L"
   ]
  },
  "packages": [
   {
    "name": "CPG236",
    "size_mm": "10x10",
    "pitch_mm": 0.5,
    "io": 106,
    "transceivers": 2
   },
   {
    "name": "CSG324",
    "size_mm": "15x15",
    "pitch_mm": 0.8,
    "io": 210,
    "transceivers": 0
   },
   {
    "name": "CSG325",
    "size_mm": "15x15",
    "pitch_mm": 0.8,
    "io": 150,
    "transceivers": 4
   },
   {
    "name": "FTG256",
    "size_mm": "17x17",
    "pitch_mm": 1.0,
    "io": 170,
    "transceivers": 0
   },
   {
    "name": "FGG484",
    "size_mm": "23x23",
    "pitch_mm": 1.0,
    "io": 250,
    "transceivers": 4
   }
  ]
 },
 "derived": {
  "lut4_equivalent": 33280,
  "lut4_equivalent_from_les": false,
  "transceiver_count": 4,
  "max_transceiver_gbps": 6.6,
  "max_pcie_gen": 2
 },
 "family_info": {
  "vendor": "AMD",
  "family": "Artix-7",
  "series": "7 Series",
  "soc": false,
  "process": "28 nm",
  "process_nm": 28,
  "configuration": "SRAM",
  "design_tool": "AMD Vivado",
  "lut_type": "LUT6",
  "logic_unit": "Logic cells",
  "dsp_type": "DSP slice",
  "large_ram_type": null,
  "source": {
   "doc": "AMD 7 Series FPGAs Product Selection Guide",
   "version": "XMP101 (v1.8)",
   "url": "https://docs.amd.com/v/u/en-US/7-series-product-selection-guide"
  },
  "url": "https://thegatearray.com/amd/artix-7/",
  "api": "https://thegatearray.com/api/amd/artix-7/"
 }
}

Errors and limits

An unknown path returns HTTP 404 (with an HTML body). There are no rate limits, but the data only changes when the site is rebuilt from new vendor documents, so please cache the responses; they are sent with a one-hour cache header.

License

The data is available under the Creative Commons Attribution 4.0 licence: you can use it in your own tools and products as long as you credit The Gate Array with a link to thegatearray.com. Values come from the vendors' selection guides and may contain extraction errors; always check the device data sheet before designing.