FPGA & adaptive SoC databook · online editionRev. 2026.10

A5D 051 vs XCZU67DR

A comparison of the Altera Agilex 5 D-Series A5D 051 and the AMD Zynq UltraScale+ RFSoC XCZU67DR using the data from both vendors' selection guides.

Side-by-side specifications

A5D 051XCZU67DR
Vendor / familyAltera Agilex 5 D-SeriesAMD Zynq UltraScale+ RFSoC
LUTs as published174,600 ALMs224,000 LUT6
LUT typeadaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)≈349,200≈358,400
CoreScore (SERV cores)——
Vendor logic figure515,070 LE489,000 SLC
DSP1,472 variable-precision DSP blocks1,872 DSP slices
Block RAM50.1 Mb22.8 Mb
Large RAM—45 Mb
Max. user I/O444154
Transceivers24 × XCVR 28 Gb/s8 × GTY 28.21 Gb/s
Hard PCI ExpressGen4 x4, Gen4 x8None
Hard processor4× Arm Cortex-A76 + Cortex-A55 (optional)4× Arm Cortex-A53
ProcessIntel 716 nm
Configuration memorySRAMSRAM
Packages01
Design toolAltera Quartus PrimeAMD Vivado

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

Both devices offer similar logic capacity: 349K and 358K LUT4 equivalents.

They use different logic architectures: the A5D 051 is built from ALMs and the XCZU67DR from LUT6, so the raw LUT counts (175K vs 224K) are not directly comparable.

For arithmetic, the XCZU67DR has 1,872 DSP slices against 1,472 variable-precision DSP blocks on the A5D 051.

The XCZU67DR has more on-chip memory (67.8 Mb vs 50.1 Mb).

Both have transceivers: 24 at up to 28 Gb/s on the A5D 051 and 8 at up to 28.21 Gb/s on the XCZU67DR.

The A5D 051 is designed with Altera Quartus Prime and the XCZU67DR with AMD Vivado.

Full specifications

See the complete spec sheets with packages and grades: A5D 051 (Agilex 5 D-Series) and XCZU67DR (Zynq UltraScale+ RFSoC).