FPGA CoreScore ranking
CoreScore is an open benchmark for FPGAs and their tools: it counts how many SERV bit-serial RISC-V cores fit in a device after synthesis and place and route. These are the 43 devices in The Gate Array with a CoreScore result, from the official CoreScore world ranking.
| # | Device | SERV cores | Board | LUTs | LUTs per core |
|---|---|---|---|---|---|
| 1 | XCVU19PAMD Virtex UltraScale+ | 10,000 | vu19p | 4,086,000 LUT6 | 409 LUT6 |
| 2 | XCVU13PAMD Virtex UltraScale+ | 8,300 | qm_xcvu13p | 1,728,000 LUT6 | 208 LUT6 |
| 3 | AGI 040Altera Agilex 7 I-Series | 8,225 | intel_dk-si-agi040fes | 1,372,000 ALMs | 167 ALMs |
| 4 | AGM 039Altera Agilex 7 M-Series | 6,666 | thunderfjord_agm039 | 1,305,600 ALMs | 196 ALMs |
| 5 | XCVU37PAMD Virtex UltraScale+ HBM | 6,000 | vcu128 | 1,304,000 LUT6 | 217 LUT6 |
| 6 | GX 2800Altera Stratix 10 GX/SX | 5,600 | intel_s10gx_devkit | 933,120 ALMs | 167 ALMs |
| 7 | AGI 027Altera Agilex 7 I-Series | 5,525 | intel_dk-si-agi027fb | 912,800 ALMs | 165 ALMs |
| 8 | XCVU9PAMD Virtex UltraScale+ | 5,087 | vcu118 | 1,182,000 LUT6 | 232 LUT6 |
| 9 | XC7VX980TAMD Virtex-7 | 3,040 | haps_dx7 | 612,000 LUT6 | 201 LUT6 |
| 10 | AGF 014Altera Agilex 7 F-Series | 2,970 | intel_dk-dev-agf014ea | 487,200 ALMs | 164 ALMs |
| 11 | 10AX115Altera Arria 10 | 2,600 | intel_a10gx_devkit | 427,200 ALMs | 164 ALMs |
| 12 | 5SGXA7Altera Stratix V | 1,568 | de5_net | 234,720 ALMs | 150 ALMs |
| 13 | A5E 065BAltera Agilex 5 E-Series | 1,327 | agilex5_dk-a5e065bb32aes1 | 222,400 ALMs | 168 ALMs |
| 14 | XC7K420TAMD Kintex-7 | 1,276 | hpc_k7 | 260,600 LUT6 | 204 LUT6 |
| 15 | 5SGSD5Altera Stratix V | 1,152 | storeypeak | 172,600 ALMs | 150 ALMs |
| 16 | XCKU5PAMD Kintex UltraScale+ | 1,085 | axku5 | 217,000 LUT6 | 200 LUT6 |
| 17 | XCKU040AMD Kintex UltraScale | 1,024 | hpc_ku | 242,400 LUT6 | 237 LUT6 |
| 18 | XC7K325TAMD Kintex-7 | 967 | genesys2 | 203,800 LUT6 | 211 LUT6 |
| 19 | XCZU7EVAMD Zynq UltraScale+ MPSoC | 940 | zcu106 | 230,000 LUT6 | 245 LUT6 |
| 20 | MPF300TMicrochip PolarFire | 882 | polarfireeval | 300,000 LUT4 | 340 LUT4 |
| 21 | XC7A200TAMD Artix-7 | 652 | nexys_video | 134,600 LUT6 | 206 LUT6 |
| 22 | XC7K160TAMD Kintex-7 | 481 | marble | 101,400 LUT6 | 211 LUT6 |
| 23 | XC7A100TAMD Artix-7 | 306 | arty_a7_100t | 63,400 LUT6 | 207 LUT6 |
| 24 | A5E 013BAltera Agilex 5 E-Series | 298 | de25_nano | 46,800 ALMs | 157 ALMs |
| 25 | 5CSXC6Altera Cyclone V | 284 | sockit | 41,910 ALMs | 148 ALMs |
| 26 | A3C 135Altera Agilex 3 | 281 | atum_a3_nano | 45,800 ALMs | 163 ALMs |
| 27 | 5CSEA6Altera Cyclone V | 271 | de10_nano | 41,910 ALMs | 155 ALMs |
| 28 | A3C 100Altera Agilex 3 | 211 | axc3000 | 34,000 ALMs | 161 ALMs |
| 29 | A5E 008BAltera Agilex 5 E-Series | 182 | axe5000 | 28,880 ALMs | 159 ALMs |
| 30 | 10M50Altera MAX 10 | 139 | deca | 50,000 LUT4 | 360 LUT4 |
| 31 | LFE5U-85Lattice ECP5 | 135 | ulx3s_85 | 84,000 LUT4 | 622 LUT4 |
| 32 | XC7A35TAMD Artix-7 | 104 | arty_a7_35t | 20,800 LUT6 | 200 LUT6 |
| 33 | XC7Z010AMD Zynq 7000 | 85 | ebaz4205 | 17,600 LUT6 | 207 LUT6 |
| 34 | 10CL025Altera Cyclone 10 LP | 64 | intel_cyc10lp_devkit | 25,000 LUT4 | 391 LUT4 |
| 35 | EP4CE22Altera Cyclone IV | 61 | de0_nano | 22,000 LUT4 | 361 LUT4 |
| 36 | LFE5U-25Lattice ECP5 | 55 | colorlight_5a75b | 24,000 LUT4 | 436 LUT4 |
| 37 | GW2AR-18Gowin Arora II | 45 | tang_nano_20k | 20,736 LUT4 | 461 LUT4 |
| 38 | 10M08Altera MAX 10 | 20 | max1000 | 8,000 LUT4 | 400 LUT4 |
| 39 | T8Efinix Trion | 17 | xyloni | — 7.4K LEs, LUTs not published | — |
| 40 | iCE40HX8KLattice iCE40 LP/HX/LM | 12 | alhambra_II | 7,680 LUT4 | 640 LUT4 |
| 41 | iCE40LP8KLattice iCE40 LP/HX/LM | 11 | tinyfpga_bx | 7,680 LUT4 | 698 LUT4 |
| 42 | iCE40UP5KLattice iCE40 UltraPlus | 10 | icebreaker | 5,280 LUT4 | 528 LUT4 |
| 43 | iCE40HX1KLattice iCE40 LP/HX/LM | 2 | go_board | 1,280 LUT4 | 640 LUT4 |
LUTs per core divides the published LUT count by the CoreScore. It shows how many logic blocks of each type one SERV core really takes, a practical way to compare LUT4, LUT6, ALM and CPE architectures. Results depend on the board, the tool version and the clock setup; when several boards use the same device, the best result is used. See how FPGA vendors count logic.