FPGA & adaptive SoC databook · online editionRev. 2026.10

CCGM1A1 vs GW2AN-18X

A comparison of the Cologne Chip GateMate CCGM1A1 and the Gowin Arora II GW2AN-18X using the data from both vendors' selection guides.

Side-by-side specifications

CCGM1A1GW2AN-18X
Vendor / familyCologne Chip GateMateGowin Arora II
LUTs as published20,480 CPEs20,736 LUT4
LUT typeCologne Chip programmable element: 8-input LUT tree, or two 4-input LUT trees4-input look-up table
LUT4 equivalent (approx.)≈40,960≈20,736
CoreScore (SERV cores)——
Vendor logic figure——
DSP— DSP blocks— 18×18 multipliers
Block RAM1.2 Mb0.5 Mb
Large RAM——
Max. user I/O162389
Transceivers1 × SerDes 5 Gb/sNone
Hard PCI ExpressNoneNone
Hard processorNoneNone
Process28 nm55 nm
Configuration memorySRAMSRAM
Packages17
Design toolYosys + nextpnr (open source)Gowin EDA

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

The CCGM1A1 has about 98% more logic capacity (41K vs 20.7K LUT4 equivalents).

They use different logic architectures: the CCGM1A1 is built from CPEs and the GW2AN-18X from LUT4, so the raw LUT counts (20.5K vs 20.7K) are not directly comparable.

The CCGM1A1 has more on-chip memory (1.2 Mb vs 0.5 Mb).

Only the CCGM1A1 has multi-gigabit transceivers (1 5 Gb/s).

The CCGM1A1 is designed with Yosys + nextpnr (open source) and the GW2AN-18X with Gowin EDA.

Full specifications

See the complete spec sheets with packages and grades: CCGM1A1 (GateMate) and GW2AN-18X (Arora II).