FPGA & adaptive SoC databook · online editionRev. 2026.10

CCGM1A1 vs GW2AN-55

A comparison of the Cologne Chip GateMate CCGM1A1 and the Gowin Arora II GW2AN-55 using the data from both vendors' selection guides.

Side-by-side specifications

CCGM1A1GW2AN-55
Vendor / familyCologne Chip GateMateGowin Arora II
LUTs as published20,480 CPEs54,720 LUT4
LUT typeCologne Chip programmable element: 8-input LUT tree, or two 4-input LUT trees4-input look-up table
LUT4 equivalent (approx.)≈40,960≈54,720
CoreScore (SERV cores)——
Vendor logic figure——
DSP— DSP blocks— 18×18 multipliers
Block RAM1.2 Mb2.5 Mb
Large RAM——
Max. user I/O162608
Transceivers1 × SerDes 5 Gb/sNone
Hard PCI ExpressNoneNone
Hard processorNoneNone
Process28 nm55 nm
Configuration memorySRAMSRAM
Packages11
Design toolYosys + nextpnr (open source)Gowin EDA

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

The GW2AN-55 has about 34% more logic capacity (54.7K vs 41K LUT4 equivalents).

They use different logic architectures: the CCGM1A1 is built from CPEs and the GW2AN-55 from LUT4, so the raw LUT counts (20.5K vs 54.7K) are not directly comparable.

The GW2AN-55 has more on-chip memory (2.5 Mb vs 1.2 Mb).

Only the CCGM1A1 has multi-gigabit transceivers (1 5 Gb/s).

The CCGM1A1 is designed with Yosys + nextpnr (open source) and the GW2AN-55 with Gowin EDA.

Full specifications

See the complete spec sheets with packages and grades: CCGM1A1 (GateMate) and GW2AN-55 (Arora II).