FPGA & adaptive SoC databook · online editionRev. 2026.10

XC7Z100

AMDZynq 7000SoC

The XC7Z100 is a Zynq 7000 SoC FPGA from AMD, built on a 28 nm process. It provides 277,400 LUT6 look-up tables (444,000 logic cells), about 443,840 LUT4 equivalents, 554,800 flip-flops, 26.5 Mb of block RAM and 2,020 DSP slices. Its processing system includes two Arm Cortex-A9 cores running at up to 1 GHz. The programmable logic offers up to 400 user I/O pins and 16 GTX transceivers at up to 12.5 Gb/s, with hard PCI Express Gen2 x8 blocks. It is available in 2 packages, from the FFG900 (31 × 31 mm) to the FFG1156 (35 × 35 mm). Temperature grades: commercial, extended, industrial. Designs are built with AMD Vivado.

444KLUT4-equivalent
277KLUTs (LUT6)
2,020DSP slices
26.5 MbBlock RAM
400Max. user I/O
16Transceivers (12.5 Gb/s)
2× A9Hard processor

Specifications

VendorAMD
FamilyZynq 7000
Series7 Series
Process28 nm
Configuration memorySRAM
LUT4-equivalent capacity443,840
Look-up tables (LUT6)277,400
Logic cells444,000
Flip-flops554,800
Block RAM26.5 Mb (755 × 36 Kb)
DSP (DSP slice)2,020
Max. user I/O400
GTX transceivers16 × 12.5 Gb/s
PCI Express (PL) Gen2 x8
Analog / monitorXADC
Hard processor2× Arm Cortex-A9 @ 1 GHz
Design toolAMD Vivado

Packages

PackageSize (mm)User I/OPS I/OTransceivers
FFG90031 × 3136212816
FFG115635 × 3540012816

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature gradeJunction rangeSpeed grades
Commercial (C)0 to 85 °C-1
Extended (E)0 to 100 °C-2
Industrial (I)−40 to 100 °C-1, -2, -2L

Alternatives to the XC7Z100

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

DeviceLUT4-eq.Vendor logicDSPBlock RAMMax I/OTransceiversPCIe
XCZU6CGAMD Zynq UltraScale+ MPSoC344K 215K LUT6469K SLC1,97325.1 Mb32824 GTH 16.3 Gb/s—
XCZU6EGAMD Zynq UltraScale+ MPSoC344K 215K LUT6469K SLC1,97325.1 Mb32824 GTH 16.3 Gb/s—
XCZU9CGAMD Zynq UltraScale+ MPSoC438K 274K LUT6600K SLC2,52032.1 Mb32824 GTH 16.3 Gb/s—
XCZU9EGAMD Zynq UltraScale+ MPSoC438K 274K LUT6600K SLC2,52032.1 Mb32824 GTH 16.3 Gb/s—
MPFS460TMicrochip PolarFire SoC461K 461K LUT4461K LE1,42028.5 Mb46820 SERDES 12.5 Gb/sGen2
Ti375Efinix Titanium363K 363K LUT4370K LE1,34427.5 Mb33716 SERDES 16 Gb/sGen4

Compare side by side: XC7Z100 vs XCZU6CG, XC7Z100 vs XCZU6EG, XC7Z100 vs XCZU9CG, XC7Z100 vs XCZU9EG, XC7Z100 vs MPFS460T.

XC7Z100 quick facts

How many LUTs does the XC7Z100 have?

The XC7Z100 has 277,400 LUT6 look-up tables, about 443,840 LUT4 equivalents (444,000 logic cells as published by AMD).

How many DSP blocks does the XC7Z100 have?

The XC7Z100 has 2,020 DSP slices and 26.5 Mb of block RAM.

Does the XC7Z100 have transceivers?

Yes, 16 GTX transceivers at up to 12.5 Gb/s.

Does the XC7Z100 have a processor?

Yes. It includes a hard 2× Arm Cortex-A9 processor.

What are the alternatives to the XC7Z100?

Devices of similar size in other families include XCZU6CG (AMD Zynq UltraScale+ MPSoC), XCZU6EG (AMD Zynq UltraScale+ MPSoC), XCZU9CG (AMD Zynq UltraScale+ MPSoC).

Which software is used to design with the XC7Z100?

Designs for the XC7Z100 are built with AMD Vivado.

Other Zynq 7000 devices

DeviceLUT4-eq.Vendor logicDSPBlock RAMMax I/OTransceiversPCIe
XC7Z007S23K 14.4K LUT623K LC661.8 Mb100——
XC7Z01028.2K 17.6K LUT628K LC802.1 Mb100——
XC7Z012S55K 34.4K LUT655K LC1202.5 Mb1504 GTP 6.25 Gb/sGen2
XC7Z014S65K 40.6K LUT665K LC1703.8 Mb200——
XC7Z01573.9K 46.2K LUT674K LC1603.3 Mb1504 GTP 6.25 Gb/sGen2
XC7Z02085.1K 53.2K LUT685K LC2204.9 Mb200——
XC7Z030126K 78.6K LUT6125K LC4009.3 Mb2504 GTX 12.5 Gb/sGen2
XC7Z035275K 172K LUT6275K LC90017.6 Mb36216 GTX 12.5 Gb/sGen2
XC7Z045350K 219K LUT6350K LC90019.2 Mb36216 GTX 12.5 Gb/sGen2
XC7Z100444K 277K LUT6444K LC2,02026.5 Mb40016 GTX 12.5 Gb/sGen2

Source: AMD Zynq 7000 SoC Product Selection Guide, XMP097 (v2.0). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.