5SGTC5 vs XCSU200P
A comparison of the Altera Stratix V 5SGTC5 and the AMD Spartan UltraScale+ XCSU200P using the data from both vendors' selection guides.
Side-by-side specifications
| 5SGTC5 | XCSU200P | |
|---|---|---|
| Vendor / family | Altera Stratix V | AMD Spartan UltraScale+ |
| LUTs as published | 160,400 ALMs | 100,000 LUT6 |
| LUT type | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈320,800 | ≈160,000 |
| CoreScore (SERV cores) | — | — |
| Vendor logic figure | 425,000 LE | 219,000 SLC |
| DSP | 256 variable-precision DSP blocks | 384 DSP slices |
| Block RAM | 45 Mb | 6.8 Mb |
| Large RAM | — | 18 Mb |
| Max. user I/O | 600 | 572 |
| Transceivers | 4 × GT 28.05 Gb/s, 32 × GX 12.5 Gb/s | 8 × GTH 16.3 Gb/s |
| Hard PCI Express | Gen3 | Gen4 x8, Gen4 x4 |
| Hard processor | None | None |
| Process | 28 nm | 16 nm |
| Configuration memory | SRAM | SRAM |
| Packages | 1 | 5 |
| Design tool | Altera Quartus Prime | AMD Vivado |
Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.
Key differences
The 5SGTC5 has about 100% more logic capacity (321K vs 160K LUT4 equivalents).
They use different logic architectures: the 5SGTC5 is built from ALMs and the XCSU200P from LUT6, so the raw LUT counts (160K vs 100K) are not directly comparable.
For arithmetic, the XCSU200P has 384 DSP slices against 256 variable-precision DSP blocks on the 5SGTC5.
The 5SGTC5 has more on-chip memory (45 Mb vs 24.8 Mb).
Both have transceivers: 36 at up to 28.05 Gb/s on the 5SGTC5 and 8 at up to 16.3 Gb/s on the XCSU200P.
The 5SGTC5 is designed with Altera Quartus Prime and the XCSU200P with AMD Vivado.
Full specifications
See the complete spec sheets with packages and grades: 5SGTC5 (Stratix V) and XCSU200P (Spartan UltraScale+).