XCSU200P

AMDSpartan UltraScale+

The XCSU200P is a Spartan UltraScale+ FPGA from AMD, built on a 16 nm process. It provides 100,000 LUT6 look-up tables (219,000 system logic cells), about 160,000 LUT4 equivalents, 200,000 flip-flops, 6.8 Mb of block RAM plus 18 Mb of UltraRAM and 384 DSP slices. It offers up to 572 user I/O pins and 8 GTH transceivers at up to 16.3 Gb/s, with hard PCI Express Gen4 x8 blocks. It is available in 5 packages, from the SBVF784 (23 × 23 mm) to the NBVA1089 (31 × 31 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.

160KLUT4-equivalent

100KLUTs (LUT6)

384DSP slices

18 MbUltraRAM

6.8 MbBlock RAM

572Max. user I/O

8Transceivers (16.3 Gb/s)

Specifications

Vendor	AMD
Family	Spartan UltraScale+
Series	UltraScale+
Process	16 nm
Configuration memory	SRAM
LUT4-equivalent capacity	160,000
Look-up tables (LUT6)	100,000
System logic cells	219,000
Flip-flops	200,000
Distributed RAM	2,038 Kb
Block RAM	6.8 Mb (192 × 36 Kb)
UltraRAM	18 Mb (64 × 288 Kb)
DSP (DSP slice)	384
Clock management tiles	6

Max. user I/O	572
HD I/O	336
HP I/O	104
XP5 I/O	132
GTH transceivers	8 × 16.3 Gb/s
PCI Express	Gen4 x8, 2× Gen4 x4
Analog / monitor	System Monitor
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
SBVF784	23 × 23	0.8	408	4
SBVG784	23 × 23	0.8	362	8
SBVF900	25 × 25	0.8	314	8
SBVA1024	27 × 27	0.8	530	8
NBVA1089	31 × 31	0.92	572	8

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Extended (E)	0 to 100 °C	-1, -2
Industrial (I)	−40 to 100 °C	-1, -2, -1L

Alternatives to the XCSU200P

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
5CGXC9Altera Cyclone V	227K 114K ALMs	301K LE	342	11.9 Mb	560	12 XCVR 3.125 Gb/s	Gen1
5CGTD9Altera Cyclone V	227K 114K ALMs	301K LE	342	11.9 Mb	560	12 XCVR 6.144 Gb/s	Gen2
Certus-N2 CT20Lattice Certus-N2	135K 135K LUT4	220K LC	520	12 Mb	298	8 SERDES 16 Gb/s	—
XC7K160TAMD Kintex-7	162K 101K LUT6	162K LC	600	11.4 Mb	400	8 GTX 12.5 Gb/s	Gen2
LAV-AT-G30Lattice Avant-G	163K 163K LUT4	262K LC	700	14.4 Mb	298	12 SERDES 12.5 Gb/s	—
LAV-AT-X30Lattice Avant-X	163K 163K LUT4	262K LC	700	14.4 Mb	298	12 SERDES 25 Gb/s	—

Compare side by side: XCSU200P vs 5CGXC9, XCSU200P vs 5CGTD9, XCSU200P vs Certus-N2 CT20.

XCSU200P quick facts

How many LUTs does the XCSU200P have?

The XCSU200P has 100,000 LUT6 look-up tables, about 160,000 LUT4 equivalents (219,000 system logic cells as published by AMD).

How many DSP blocks does the XCSU200P have?

The XCSU200P has 384 DSP slices and 6.8 Mb of block RAM plus 18 Mb of UltraRAM.

Does the XCSU200P have transceivers?

Yes, 8 GTH transceivers at up to 16.3 Gb/s.

What are the alternatives to the XCSU200P?

Devices of similar size in other families include 5CGXC9 (Altera Cyclone V), 5CGTD9 (Altera Cyclone V), Certus-N2 CT20 (Lattice Certus-N2).

Which software is used to design with the XCSU200P?

Designs for the XCSU200P are built with AMD Vivado.

Other Spartan UltraScale+ devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XCSU10P	8K 5K LUT6	11K SLC	24	1.7 Mb	304	—	—
XCSU25P	16K 10K LUT6	22K SLC	36	1.7 Mb	304	—	—
XCSU35P	25.6K 16K LUT6	36K SLC	48	1.7 Mb	304	—	—
XCSU45P	38.4K 24K LUT6	53K SLC	96	2.5 Mb	262	4 GTH 16.3 Gb/s	Gen4
XCSU60P	48K 30K LUT6	66K SLC	144	3.4 Mb	262	4 GTH 16.3 Gb/s	Gen4
XCSU65P	48K 30K LUT6	66K SLC	144	3.8 Mb	478	4 GTH 16.3 Gb/s	Gen4
XCSU100P	73.6K 46K LUT6	101K SLC	144	5.1 Mb	478	4 GTH 16.3 Gb/s	Gen4
XCSU150P	101K 63K LUT6	138K SLC	384	5.9 Mb	572	8 GTH 16.3 Gb/s	Gen4
XCSU200P	160K 100K LUT6	219K SLC	384	6.8 Mb	572	8 GTH 16.3 Gb/s	Gen4

Source: AMD UltraScale+ FPGAs Product Selection Guide, XMP103 (v2.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.