FPGA & adaptive SoC databook · online editionRev. 2026.10

A3C 025 vs M2S010

A comparison of the Altera Agilex 3 A3C 025 and the Microchip SmartFusion2 M2S010 using the data from both vendors' selection guides.

Side-by-side specifications

A3C 025M2S010
Vendor / familyAltera Agilex 3Microchip SmartFusion2
LUTs as published8,500 ALMs12,084 LUT4
LUT typeadaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)4-input look-up table
LUT4 equivalent (approx.)≈17,000≈12,084
CoreScore (SERV cores)——
Vendor logic figure25,075 LE12,084 LE
DSP34 variable-precision DSP blocks22 18×18 math blocks (MACC)
Block RAM1.3 Mb0.4 Mb
Large RAM——
Max. user I/O256233
TransceiversNone4 × SERDES 5 Gb/s
Hard PCI ExpressNoneGen2
Hard processor2× Arm Cortex-A55 (optional)1× Arm Cortex-M3
ProcessIntel 765 nm
Configuration memorySRAMNon-volatile (flash)
Packages34
Design toolAltera Quartus PrimeMicrochip Libero SoC

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

The A3C 025 has about 41% more logic capacity (17K vs 12.1K LUT4 equivalents).

They use different logic architectures: the A3C 025 is built from ALMs and the M2S010 from LUT4, so the raw LUT counts (8.5K vs 12.1K) are not directly comparable.

For arithmetic, the A3C 025 has 34 variable-precision DSP blocks against 22 18×18 math blocks (MACC) on the M2S010.

The A3C 025 has more on-chip memory (1.3 Mb vs 0.4 Mb).

Only the M2S010 has multi-gigabit transceivers (4 5 Gb/s).

Configuration memory: sram on the A3C 025, non-volatile (flash) on the M2S010.

The A3C 025 is designed with Altera Quartus Prime and the M2S010 with Microchip Libero SoC.

Full specifications

See the complete spec sheets with packages and grades: A3C 025 (Agilex 3) and M2S010 (SmartFusion2).