FPGA & adaptive SoC databook · online editionRev. 2026.10

Mach-N2 MH06 vs XCSU60P

A comparison of the Lattice Mach-N2 Mach-N2 MH06 and the AMD Spartan UltraScale+ XCSU60P using the data from both vendors' selection guides.

Side-by-side specifications

Mach-N2 MH06XCSU60P
Vendor / familyLattice Mach-N2AMD Spartan UltraScale+
LUTs as published40,000 LUT430,000 LUT6
LUT type4-input look-up table6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)≈40,000≈48,000
CoreScore (SERV cores)——
Vendor logic figure65,000 LC66,000 SLC
DSP120 18×18 multipliers144 DSP slices
Block RAM4 Mb3.4 Mb
Large RAM——
Max. user I/O196262
Transceivers4 × SERDES 16 Gb/s4 × GTH 16.3 Gb/s
Hard PCI ExpressNoneGen4 x4
Hard processorNoneNone
Process16 nm16 nm
Configuration memoryInternal flashSRAM
Packages23
Design toolLattice RadiantAMD Vivado

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

The XCSU60P has about 20% more logic capacity (48K vs 40K LUT4 equivalents).

They use different logic architectures: the Mach-N2 MH06 is built from LUT4 and the XCSU60P from LUT6, so the raw LUT counts (40K vs 30K) are not directly comparable.

For arithmetic, the XCSU60P has 144 DSP slices against 120 18×18 multipliers on the Mach-N2 MH06.

The Mach-N2 MH06 has more on-chip memory (4 Mb vs 3.4 Mb).

Both have transceivers: 4 at up to 16 Gb/s on the Mach-N2 MH06 and 4 at up to 16.3 Gb/s on the XCSU60P.

Configuration memory: internal flash on the Mach-N2 MH06, sram on the XCSU60P.

The Mach-N2 MH06 is designed with Lattice Radiant and the XCSU60P with AMD Vivado.

Full specifications

See the complete spec sheets with packages and grades: Mach-N2 MH06 (Mach-N2) and XCSU60P (Spartan UltraScale+).