SX 2100

AlteraStratix 10 GX/SXSoC

The SX 2100 is a Stratix 10 GX/SX SoC FPGA from Altera, built on a 14 nm process. It provides 679,680 adaptive logic modules (ALMs) (2,005,000 logic elements (LEs)), about 1,359,360 LUT4 equivalents, 127 Mb of block RAM and 3,744 variable-precision DSP blocks. Its processing system includes four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 704 user I/O pins and 96 XCVR/XCVR transceivers at up to 28.3 Gb/s, with hard PCI Express Gen3 x16 blocks. It is available in 2 packages, from the F1760 (42.5 × 42.5 mm) to the F2397 (50 × 50 mm). Designs are built with Altera Quartus Prime.

1359KLUT4-equivalent

680KALMs

3,744variable-precision DSP blocks

127 MbBlock RAM

704Max. user I/O

96Transceivers (28.3 Gb/s)

4× A53Hard processor

Specifications

Vendor	Altera
Family	Stratix 10 GX/SX
Series	Stratix
Process	14 nm
Configuration memory	SRAM
LUT4-equivalent capacity	1,359,360
Adaptive logic modules (ALMs)	679,680
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
Logic elements (LEs)	2,005,000
Distributed RAM	11,264 Kb
Block RAM	127 Mb (6501 × 20 Kb)
DSP (variable-precision DSP block)	3,744

Max. user I/O	704
XCVR transceivers	64 × 28.3 Gb/s
XCVR transceivers	32 × 17.4 Gb/s
PCI Express (PL)	4× Gen3 x16
Analog / monitor	None
Hard processor	4× Arm Cortex-A53 @ 1.5 GHz
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F1760	42.5 × 42.5	1.0	688	48
F2397	50 × 50	1.0	704	96

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the SX 2100

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
A5D 160Altera Agilex 5 D-Series	1096K 548K ALMs	1617K LE	4,968	156.4 Mb	888	48 XCVR 28 Gb/s	Gen4
A5D 130Altera Agilex 5 D-Series	877K 438K ALMs	1293K LE	3,864	125.2 Mb	888	48 XCVR 28 Gb/s	Gen4
Ti2000Efinix Titanium	≈1974K 1974K LEs	1974K LE	3,808	117 Mb	480	40 SERDES 25.8 Gb/s	Gen4
Ti1600Efinix Titanium	≈1578K 1578K LEs	1578K LE	3,050	93.6 Mb	480	40 SERDES 25.8 Gb/s	Gen4
AGF 014Altera Agilex 7 F-Series	974K 487K ALMs	1437K LE	4,510	139 Mb	768	32 XCVR 58 Gb/s	—
AGI 022Altera Agilex 7 I-Series	1497K 748K ALMs	2208K LE	6,250	212 Mb	720	64 XCVR 116 Gb/s	—

Compare side by side: SX 2100 vs A5D 160, SX 2100 vs A5D 130, SX 2100 vs Ti2000, SX 2100 vs Ti1600.

SX 2100 quick facts

How many LUTs does the SX 2100 have?

The SX 2100 has 679,680 adaptive logic modules (ALMs), about 1,359,360 LUT4 equivalents (2,005,000 logic elements (les) as published by Altera).

How many DSP blocks does the SX 2100 have?

The SX 2100 has 3,744 variable-precision DSP blocks and 127 Mb of block RAM.

Does the SX 2100 have transceivers?

Yes, 96 XCVR/XCVR transceivers at up to 28.3 Gb/s.

Does the SX 2100 have a processor?

Yes. It includes a hard 4× Arm Cortex-A53 processor.

What are the alternatives to the SX 2100?

Devices of similar size in other families include A5D 160 (Altera Agilex 5 D-Series), A5D 130 (Altera Agilex 5 D-Series), Ti2000 (Efinix Titanium).

Which software is used to design with the SX 2100?

Designs for the SX 2100 are built with Altera Quartus Prime.

Other Stratix 10 GX/SX devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
GX 400	256K 128K ALMs	378K LE	648	30 Mb	374	24 XCVR/XCVR 28.3 Gb/s	Gen3
SX 400	256K 128K ALMs	378K LE	648	30 Mb	374	24 XCVR/XCVR 28.3 Gb/s	Gen3
GX 650	415K 207K ALMs	612K LE	1,152	49 Mb	392	24 XCVR/XCVR 28.3 Gb/s	Gen3
SX 650	415K 207K ALMs	612K LE	1,152	49 Mb	392	24 XCVR/XCVR 28.3 Gb/s	Gen3
GX 850	570K 285K ALMs	841K LE	2,016	68 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3
SX 850	570K 285K ALMs	841K LE	2,016	68 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3
GX 1100	899K 449K ALMs	1325K LE	2,592	107 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3
SX 1100	899K 449K ALMs	1325K LE	2,592	107 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3
GX 1650	1101K 551K ALMs	1624K LE	3,145	114 Mb	704	96 XCVR/XCVR 28.3 Gb/s	Gen3
SX 1650	1101K 551K ALMs	1624K LE	3,145	114 Mb	704	96 XCVR/XCVR 28.3 Gb/s	Gen3
GX 2100	1359K 680K ALMs	2005K LE	3,744	127 Mb	704	96 XCVR/XCVR 28.3 Gb/s	Gen3
SX 2100	1359K 680K ALMs	2005K LE	3,744	127 Mb	704	96 XCVR/XCVR 28.3 Gb/s	Gen3
GX 2500	1642K 821K ALMs	2422K LE	5,011	195 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3
SX 2500	1642K 821K ALMs	2422K LE	5,011	195 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3
GX 2800	1866K 933K ALMs	2753K LE	5,760	229 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3
SX 2800	1866K 933K ALMs	2753K LE	5,760	229 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3

Source: Altera Stratix 10 GX/SX FPGA Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.