10AX115

AlteraArria 10SoC

The 10AX115 is an Arria 10 FPGA from Altera, built on a 20 nm process. It provides 427,200 adaptive logic modules (ALMs) (1,506,000 logic elements (LEs)), about 854,400 LUT4 equivalents, 1,708,800 flip-flops, 53 Mb of block RAM and 1,518 variable-precision DSP blocks. It offers up to 768 user I/O pins and 96 XCVR transceivers at up to 17.4 Gb/s, with hard PCI Express Gen3 x8 blocks. It is available in 3 packages, from the F1152 (35 × 35 mm) to the F1932 (45 × 45 mm). Designs are built with Altera Quartus Prime.

854KLUT4-equivalent

427KALMs

1,518variable-precision DSP blocks

53 MbBlock RAM

768Max. user I/O

96Transceivers (17.4 Gb/s)

Specifications

Vendor	Altera
Family	Arria 10
Series	Arria
Process	20 nm
Configuration memory	SRAM
LUT4-equivalent capacity	854,400
Adaptive logic modules (ALMs)	427,200
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
Logic elements (LEs)	1,506,000
Flip-flops	1,708,800
Block RAM	53 Mb (2713 × 20 Kb)
DSP (variable-precision DSP block)	1,518

Max. user I/O	768
XCVR transceivers	96 × 17.4 Gb/s
PCI Express	4× Gen3 x8
Analog / monitor	None
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	User I/O	Transceivers
F1152	35 × 35	504	24
F1517	40 × 40	600	48
F1932	45 × 45	768	48

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the 10AX115

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XCKU15PAMD Kintex UltraScale+	837K 523K LUT6	1143K SLC	1,968	34.6 Mb	668	76 GTH/GTY 32.75 Gb/s	Gen3
GX 850Altera Stratix 10 GX/SX	570K 285K ALMs	841K LE	2,016	68 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3
XC7VH580TAMD Virtex-7	580K 363K LUT6	580K LC	1,680	33 Mb	600	56 GTH/GTZ 28.05 Gb/s	Gen3
XC7VH870TAMD Virtex-7	876K 548K LUT6	876K LC	2,520	49.6 Mb	300	88 GTH/GTZ 28.05 Gb/s	Gen3
XC7VX550TAMD Virtex-7	554K 346K LUT6	554K LC	2,880	41.5 Mb	600	80 GTH 13.1 Gb/s	Gen3
XC7VX980TAMD Virtex-7	979K 612K LUT6	979K LC	3,600	52.7 Mb	900	72 GTH 13.1 Gb/s	Gen3

Compare side by side: 10AX115 vs XCKU15P, 10AX115 vs GX 850, 10AX115 vs XC7VH580T.

10AX115 quick facts

How many LUTs does the 10AX115 have?

The 10AX115 has 427,200 adaptive logic modules (ALMs), about 854,400 LUT4 equivalents (1,506,000 logic elements (les) as published by Altera).

How many DSP blocks does the 10AX115 have?

The 10AX115 has 1,518 variable-precision DSP blocks and 53 Mb of block RAM.

Does the 10AX115 have transceivers?

Yes, 96 XCVR transceivers at up to 17.4 Gb/s.

What are the alternatives to the 10AX115?

Devices of similar size in other families include XCKU15P (AMD Kintex UltraScale+), GX 850 (Altera Stratix 10 GX/SX), XC7VH580T (AMD Virtex-7).

Which software is used to design with the 10AX115?

Designs for the 10AX115 are built with Altera Quartus Prime.

Other Arria 10 devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
10AX016	123K 61.5K ALMs	210K LE	156	8.6 Mb	288	12 XCVR 17.4 Gb/s	Gen3
10AX022	167K 83.7K ALMs	288K LE	192	11.5 Mb	288	12 XCVR 17.4 Gb/s	Gen3
10AX027	203K 102K ALMs	354K LE	830	14.7 Mb	384	24 XCVR 17.4 Gb/s	Gen3
10AX032	237K 119K ALMs	419K LE	985	17.4 Mb	384	24 XCVR 17.4 Gb/s	Gen3
10AX048	364K 182K ALMs	629K LE	1,368	28.1 Mb	492	36 XCVR 17.4 Gb/s	Gen3
10AX057	434K 217K ALMs	747K LE	1,523	35.2 Mb	696	48 XCVR 17.4 Gb/s	Gen3
10AX066	501K 251K ALMs	865K LE	1,687	41.7 Mb	696	48 XCVR 17.4 Gb/s	Gen3
10AX090	679K 340K ALMs	1180K LE	1,518	47.3 Mb	768	96 XCVR 17.4 Gb/s	Gen3
10AT090	679K 340K ALMs	1180K LE	1,518	47.3 Mb	624	78 XCVR/XCVR 25.78 Gb/s	Gen3
10AX115	854K 427K ALMs	1506K LE	1,518	53 Mb	768	96 XCVR 17.4 Gb/s	Gen3
10AT115	854K 427K ALMs	1506K LE	1,518	53 Mb	624	78 XCVR/XCVR 25.78 Gb/s	Gen3

Source: Altera Arria 10 FPGA and SoC Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.