XC7VH870T

AMDVirtex-7

The XC7VH870T is a Virtex-7 FPGA from AMD, built on a 28 nm process. It provides 547,600 LUT6 look-up tables (876,160 logic cells), 1,095,200 flip-flops, 49.6 Mb of block RAM and 2,520 DSP slices. It offers up to 300 user I/O pins and 88 GTH/GTZ transceivers at up to 28.05 Gb/s, with hard PCI Express Gen3 blocks. It comes in a single package, the FLG1932 (45 × 45 mm). Temperature grades: commercial, extended. Designs are built with AMD Vivado.

876KLUT4-equivalent

548KLUTs (LUT6)

2,520DSP slices

49.6 MbBlock RAM

300Max. user I/O

88Transceivers (28.05 Gb/s)

Specifications

Vendor	AMD
Family	Virtex-7
Series	7 Series
Process	28 nm
Configuration memory	SRAM
LUT4-equivalent capacity	876,160
Look-up tables (LUT6)	547,600
Logic cells	876,160
Flip-flops	1,095,200
Distributed RAM	13,275 Kb
Block RAM	49.6 Mb (1410 × 36 Kb)
DSP (DSP slice)	2,520
Clock management tiles	18

Max. user I/O	300
Differential pairs	144
GTH transceivers	72 × 13.1 Gb/s
GTZ transceivers	16 × 28.05 Gb/s
PCI Express	3× Gen3
Analog / monitor	XADC
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
FLG1932	45 × 45	1.0	300	88

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-1, -2
Extended (E)	0 to 100 °C	-2L, -2G

Alternatives to the XC7VH870T

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XCKU15PAMD Kintex UltraScale+	837K 523K LUT6	1143K SLC	1,968	34.6 Mb	668	76 GTH/GTY 32.75 Gb/s	Gen3
10AT115Altera Arria 10	854K 427K ALMs	1506K LE	1,518	53 Mb	624	78 XCVR/XCVR 25.78 Gb/s	Gen3
10AT090Altera Arria 10	679K 340K ALMs	1180K LE	1,518	47.3 Mb	624	78 XCVR/XCVR 25.78 Gb/s	Gen3
10AX115Altera Arria 10	854K 427K ALMs	1506K LE	1,518	53 Mb	768	96 XCVR 17.4 Gb/s	Gen3
XCKU11PAMD Kintex UltraScale+	478K 299K LUT6	653K SLC	2,928	21.1 Mb	512	52 GTH/GTY 32.75 Gb/s	Gen3
10AX090Altera Arria 10	679K 340K ALMs	1180K LE	1,518	47.3 Mb	768	96 XCVR 17.4 Gb/s	Gen3

Compare side by side: XC7VH870T vs XCKU15P, XC7VH870T vs 10AT115, XC7VH870T vs 10AT090.

XC7VH870T quick facts

How many LUTs does the XC7VH870T have?

The XC7VH870T has 547,600 LUT6 look-up tables, about 876,160 LUT4 equivalents (876,160 logic cells as published by AMD).

How many DSP blocks does the XC7VH870T have?

The XC7VH870T has 2,520 DSP slices and 49.6 Mb of block RAM.

Does the XC7VH870T have transceivers?

Yes, 88 GTH/GTZ transceivers at up to 28.05 Gb/s.

What are the alternatives to the XC7VH870T?

Devices of similar size in other families include XCKU15P (AMD Kintex UltraScale+), 10AT115 (Altera Arria 10), 10AT090 (Altera Arria 10).

Which software is used to design with the XC7VH870T?

Designs for the XC7VH870T are built with AMD Vivado.

Other Virtex-7 devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XC7VX330T	326K 204K LUT6	326K LC	1,120	26.4 Mb	700	28 GTH 13.1 Gb/s	Gen3
XC7VX415T	412K 258K LUT6	412K LC	2,160	30.9 Mb	600	48 GTH 13.1 Gb/s	Gen3
XC7VX485T	486K 304K LUT6	486K LC	2,800	36.2 Mb	700	56 GTX 12.5 Gb/s	Gen2
XC7VX550T	554K 346K LUT6	554K LC	2,880	41.5 Mb	600	80 GTH 13.1 Gb/s	Gen3
XC7VH580T	580K 363K LUT6	580K LC	1,680	33 Mb	600	56 GTH/GTZ 28.05 Gb/s	Gen3
XC7V585T	583K 364K LUT6	583K LC	1,260	27.9 Mb	850	36 GTX 12.5 Gb/s	Gen2
XC7VX690T	693K 433K LUT6	693K LC	3,600	51.7 Mb	1,000	80 GTH 13.1 Gb/s	Gen3
XC7VH870T	876K 548K LUT6	876K LC	2,520	49.6 Mb	300	88 GTH/GTZ 28.05 Gb/s	Gen3
XC7VX980T	979K 612K LUT6	979K LC	3,600	52.7 Mb	900	72 GTH 13.1 Gb/s	Gen3
XC7VX1140T	1139K 712K LUT6	1139K LC	3,360	66.1 Mb	1,100	96 GTH 13.1 Gb/s	Gen3
XC7V2000T	1955K 1222K LUT6	1955K LC	2,160	45.4 Mb	1,200	36 GTX 12.5 Gb/s	Gen2

Source: AMD 7 Series FPGAs Product Selection Guide, XMP101 (v1.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.