Cologne Chip GateMate FPGAs
The Cologne Chip GateMate family has 6 devices, built on the 28 nm process, ranging from 20.5K CPEs to 512K CPEs and from none to — DSP blocks. It uses CPEs (8-input LUT trees). Transceivers: SerDes, up to 5 Gb/s.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| CCGM1A1 | 20,480 CPEs | — | — | 1.2 Mb | 162 | 1 SerDes 5 Gb/s | — | — |
| CCGM1A2 | 40,960 CPEs | — | — | 2.5 Mb | 162 | 2 SerDes 5 Gb/s | — | — |
| CCGM1A4 | 81,920 CPEs | — | — | 5 Mb | 154 | 4 SerDes 5 Gb/s | — | — |
| CCGM1A9 | 184,320 CPEs | — | — | 11.2 Mb | 1,458 | 9 SerDes 5 Gb/s | — | — |
| CCGM1A16 | 327,680 CPEs | — | — | 20 Mb | 2,592 | 16 SerDes 5 Gb/s | — | — |
| CCGM1A25 | 512,000 CPEs | — | — | 31.2 Mb | 4,050 | 25 SerDes 5 Gb/s | — | — |
Source: Cologne Chip GateMate product table, retrieved 2026-10-26.