FPGA & adaptive SoC databook · online editionRev. 2026.10

5AGTC3 vs Mach-N2 MH20

A comparison of the Altera Arria V 5AGTC3 and the Lattice Mach-N2 Mach-N2 MH20 using the data from both vendors' selection guides.

Side-by-side specifications

5AGTC3Mach-N2 MH20
Vendor / familyAltera Arria VLattice Mach-N2
LUTs as published58,900 ALMs135,000 LUT4
LUT typeadaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)4-input look-up table
LUT4 equivalent (approx.)≈117,800≈135,000
CoreScore (SERV cores)——
Vendor logic figure156,000 LE220,000 LC
DSP396 variable-precision DSP blocks520 18×18 multipliers
Block RAM10.3 Mb12 Mb
Large RAM——
Max. user I/O416248
Transceivers3 × XCVR 6.5536 Gb/s, 4 × XCVR 10.3125 Gb/s4 × SERDES 16 Gb/s
Hard PCI ExpressGen2 x4None
Hard processorNoneNone
Process28 nm16 nm
Configuration memorySRAMInternal flash
Packages21
Design toolAltera Quartus PrimeLattice Radiant

Highlighted values are higher. LUT counts are shown as published; the LUT4 equivalent is an approximation to compare different LUT types, see how FPGA vendors count logic. Add up to two more devices to this comparison.

Key differences

The Mach-N2 MH20 has about 15% more logic capacity (135K vs 118K LUT4 equivalents).

They use different logic architectures: the 5AGTC3 is built from ALMs and the Mach-N2 MH20 from LUT4, so the raw LUT counts (58.9K vs 135K) are not directly comparable.

For arithmetic, the Mach-N2 MH20 has 520 18×18 multipliers against 396 variable-precision DSP blocks on the 5AGTC3.

The Mach-N2 MH20 has more on-chip memory (12 Mb vs 10.3 Mb).

Both have transceivers: 7 at up to 10.3125 Gb/s on the 5AGTC3 and 4 at up to 16 Gb/s on the Mach-N2 MH20.

Configuration memory: sram on the 5AGTC3, internal flash on the Mach-N2 MH20.

The 5AGTC3 is designed with Altera Quartus Prime and the Mach-N2 MH20 with Lattice Radiant.

Full specifications

See the complete spec sheets with packages and grades: 5AGTC3 (Arria V) and Mach-N2 MH20 (Mach-N2).