5AGTC3

The 5AGTC3 is an Arria V FPGA from Altera, built on a 28 nm process. It provides 58,900 adaptive logic modules (ALMs) (156,000 logic elements (LEs)), 235,600 flip-flops, 10.3 Mb of block RAM and 396 variable-precision DSP blocks. It offers up to 416 user I/O pins and 7 XCVR/XCVR transceivers at up to 10.3125 Gb/s, with hard PCI Express Gen2 x4 blocks. It is available in 2 packages, from the F672 (27 × 27 mm) to the F896 (31 × 31 mm). Designs are built with Altera Quartus Prime.

Specifications

Packages

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the 5AGTC3

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Compare side by side: 5AGTC3 vs XCSU150P, 5AGTC3 vs Certus-N2 CT16, 5AGTC3 vs Certus-N2 CT20, 5AGTC3 vs Mach-N2 MH16.

Compare the 5AGTC3 with up to three other FPGAs.

5AGTC3 quick facts

How many LUTs does the 5AGTC3 have?

The 5AGTC3 has 58,900 adaptive logic modules (ALMs) (156,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the 5AGTC3 have?

The 5AGTC3 has 396 variable-precision DSP blocks and 10.3 Mb of block RAM.

Does the 5AGTC3 have transceivers?

Yes, 7 XCVR/XCVR transceivers at up to 10.3125 Gb/s.

What are the alternatives to the 5AGTC3?

Devices of similar size in other families include XCSU150P (AMD Spartan UltraScale+), Certus-N2 CT16 (Lattice Certus-N2), Certus-N2 CT20 (Lattice Certus-N2).

Which software is used to design with the 5AGTC3?

Designs for the 5AGTC3 are built with Altera Quartus Prime.

Other Arria V devices

Source: Altera Arria V FPGA and SoC Product Table, 2025.12.04. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.