FPGA & adaptive SoC databook · online editionRev. 2026.10

Gowin Arora V FPGAs

The Gowin Arora V family has 12 devices, built on the 22 nm process, ranging from 15.1K LUT4 to 138K LUT4 and from 28 to 298 27×18 DSP blocks. It uses LUT4 look-up tables. Transceivers: SERDES, up to 12.5 Gb/s.

DeviceLUT4-eq.Vendor logicDSPBlock RAMMax I/OTransceiversPCIe
GW5AT-1515.1K 15.1K LUT4—280.6 Mb534 SERDES 12.5 Gb/sGen3
GW5ART-1515.1K 15.1K LUT4—280.6 Mb534 SERDES 12.5 Gb/sGen3
GW5A-2523K 23K LUT4—281 Mb239——
GW5AR-2523K 23K LUT4—281 Mb239——
GW5AS-2523K 23K LUT4—281 Mb239——
GW5A-6059.9K 59.9K LUT4—1182.1 Mb320——
GW5AT-6059.9K 59.9K LUT4—1182.1 Mb3204 SERDES 12.5 Gb/sGen3
GW5AT-7586.7K 86.7K LUT4—2134.5 Mb3128 SERDES 12.5 Gb/sGen3
GW5A-138138K 138K LUT4—2986 Mb312——
GW5AT-138138K 138K LUT4—2986 Mb3128 SERDES 12.5 Gb/sGen3
GW5AS-138138K 138K LUT4—2986 Mb312——
GW5AST-138138K 138K LUT4—2986 Mb3768 SERDES 12.5 Gb/sGen3

Source: Gowin Arora V product page, retrieved 2026-10-24.