XC2VE3304

AMDVersal AI Edge Gen 2SoC

The XC2VE3304 is a Versal AI Edge Gen 2 SoC FPGA from AMD. It provides 94,592 LUT6 look-up tables (206,920 system logic cells), 189,184 flip-flops, 5 Mb of block RAM plus 13.2 Mb of UltraRAM and 184 DSP Engines. Its processing system includes four Arm Cortex-A78AE cores, a Arm Cortex-R52 real-time processor. The programmable logic offers up to 308 user I/O pins and 4 GTYP transceivers at up to 32.75 Gb/s, with hard PCI Express Gen5 x4 blocks. It is available in 2 packages, from the SFVA1089 ( mm) to the SSVA1440 ( mm). Designs are built with AMD Vivado.

94,592LUTs (LUT6)

184DSP Engines

5 MbBlock RAM

13.2 MbUltraRAM

308Max. user I/O

4Transceivers (32.75 Gb/s)

4× A78AEHard processor

Specifications

Vendor	AMD
Family	Versal AI Edge Gen 2
Series	Versal
Configuration memory	SRAM
Look-up tables (LUT6)	94,592
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈151,347
System logic cells	206,920
Flip-flops	189,184
Distributed RAM	2,970 Kb
Block RAM	5 Mb
UltraRAM	13.2 Mb
AI Engines	24 AI Engine-ML tiles
DSP (DSP Engine)	184

Max. user I/O	308
GTYP transceivers	4 × 32.75 Gb/s
PCI Express (PL)	Gen5 x4
Analog / monitor	System Monitor
Hard processor	4× Arm Cortex-A78AE
Real-time processor	Arm Cortex-R52
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	PS I/O	Transceivers
SFVA1089		0.8	278	78	12
SSVA1440		0.8	308	78	12

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the XC2VE3304

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC2VM3358AMD Versal Prime Gen 2	94,592 LUT6	207K SLC	184	5 Mb	308	4 GTYP 32.75 Gb/s	Gen5	—
XCVE2202AMD Versal AI Edge	105,000 LUT6	230K SLC	324	3.8 Mb	238	8 GTYP 32.75 Gb/s	Gen4	—
A5E 028AAltera Agilex 5 E-Series	95,680 ALMs	282K LE	376	14 Mb	392	12 XCVR 28 Gb/s	Gen4	—
A5E 028BAltera Agilex 5 E-Series	95,680 ALMs	282K LE	376	14 Mb	392	12 XCVR 17 Gb/s	Gen4	—
A5E 013AAltera Agilex 5 E-Series	46,800 ALMs	138K LE	188	7 Mb	392	4 XCVR 28 Gb/s	Gen4	—
A5E 013BAltera Agilex 5 E-Series	46,800 ALMs	138K LE	188	7 Mb	392	4 XCVR 17 Gb/s	Gen4	298 de25_nano

Compare side by side: XC2VE3304 vs XC2VM3358, XC2VE3304 vs XCVE2202, XC2VE3304 vs A5E 028A.

Compare the XC2VE3304 with up to three other FPGAs.

XC2VE3304 quick facts

How many LUTs does the XC2VE3304 have?

The XC2VE3304 has 94,592 LUT6 look-up tables (206,920 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC2VE3304 have?

The XC2VE3304 has 184 DSP Engines and 5 Mb of block RAM plus 13.2 Mb of UltraRAM.

Does the XC2VE3304 have transceivers?

Yes, 4 GTYP transceivers at up to 32.75 Gb/s.

Does the XC2VE3304 have a processor?

Yes. It includes a hard 4× Arm Cortex-A78AE processor.

What are the alternatives to the XC2VE3304?

Devices of similar size in other families include XC2VM3358 (AMD Versal Prime Gen 2), XCVE2202 (AMD Versal AI Edge), A5E 028A (Altera Agilex 5 E-Series).

Which software is used to design with the XC2VE3304?

Designs for the XC2VE3304 are built with AMD Vivado.

Other Versal AI Edge Gen 2 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC2VE3304	94,592 LUT6	207K SLC	184	5 Mb	308	4 GTYP 32.75 Gb/s	Gen5	—
XC2VE3358	94,592 LUT6	207K SLC	184	5 Mb	308	4 GTYP 32.75 Gb/s	Gen5	—
XC2VE3504	225,000 LUT6	492K SLC	700	13.6 Mb	428	12 GTYP 32.75 Gb/s	Gen5	—
XC2VE3558	225,000 LUT6	492K SLC	700	13.6 Mb	428	12 GTYP 32.75 Gb/s	Gen5	—
XC2VE3804	543,104 LUT6	1188K SLC	2,064	47.2 Mb	556	20 GTYP 32.75 Gb/s	Gen5	—
XC2VE3858	543,104 LUT6	1188K SLC	2,064	47.2 Mb	556	20 GTYP 32.75 Gb/s	Gen5	—

Source: AMD Versal AI Edge Gen 2 Series Product Selection Guide, XMP505 (v1.5). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.