XC7V585T

AMDVirtex-7

The XC7V585T is a Virtex-7 FPGA from AMD, built on a 28 nm process. It provides 364,200 LUT6 look-up tables (582,720 logic cells), 728,400 flip-flops, 27.9 Mb of block RAM and 1,260 DSP slices. It offers up to 850 user I/O pins and 36 GTX transceivers at up to 12.5 Gb/s, with hard PCI Express Gen2 blocks. It is available in 2 packages, from the FFG1157 (35 × 35 mm) to the FFG1761 (42.5 × 42.5 mm). Temperature grades: commercial, extended, industrial. Designs are built with AMD Vivado.

583KLUT4-equivalent

364KLUTs (LUT6)

1,260DSP slices

27.9 MbBlock RAM

850Max. user I/O

36Transceivers (12.5 Gb/s)

Specifications

Vendor	AMD
Family	Virtex-7
Series	7 Series
Process	28 nm
Configuration memory	SRAM
LUT4-equivalent capacity	582,720
Look-up tables (LUT6)	364,200
Logic cells	582,720
Flip-flops	728,400
Distributed RAM	6,938 Kb
Block RAM	27.9 Mb (795 × 36 Kb)
DSP (DSP slice)	1,260
Clock management tiles	18

Max. user I/O	850
Differential pairs	408
GTX transceivers	36 × 12.5 Gb/s
PCI Express	3× Gen2
Analog / monitor	XADC
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
FFG1157	35 × 35	1.0	600	20
FFG1761	42.5 × 42.5	1.0	850	36

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	-1, -2
Extended (E)	0 to 100 °C	-2L, -3
Industrial (I)	−40 to 100 °C	-1, -2

Alternatives to the XC7V585T

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
MPF500TMicrochip PolarFire	481K 481K LUT4	481K LE	1,480	29.7 Mb	584	24 SERDES 12.7 Gb/s	Gen2
10AX057Altera Arria 10	434K 217K ALMs	747K LE	1,523	35.2 Mb	696	48 XCVR 17.4 Gb/s	Gen3
10AX066Altera Arria 10	501K 251K ALMs	865K LE	1,687	41.7 Mb	696	48 XCVR 17.4 Gb/s	Gen3
10AX048Altera Arria 10	364K 182K ALMs	629K LE	1,368	28.1 Mb	492	36 XCVR 17.4 Gb/s	Gen3
XC7K420TAMD Kintex-7	417K 261K LUT6	417K LC	1,680	29.4 Mb	400	32 GTX 12.5 Gb/s	Gen2
LAV-AT-G70Lattice Avant-G	397K 397K LUT4	637K LC	1,800	35.6 Mb	554	28 SERDES 12.5 Gb/s	—

Compare side by side: XC7V585T vs MPF500T, XC7V585T vs 10AX057, XC7V585T vs 10AX066.

XC7V585T quick facts

How many LUTs does the XC7V585T have?

The XC7V585T has 364,200 LUT6 look-up tables, about 582,720 LUT4 equivalents (582,720 logic cells as published by AMD).

How many DSP blocks does the XC7V585T have?

The XC7V585T has 1,260 DSP slices and 27.9 Mb of block RAM.

Does the XC7V585T have transceivers?

Yes, 36 GTX transceivers at up to 12.5 Gb/s.

What are the alternatives to the XC7V585T?

Devices of similar size in other families include MPF500T (Microchip PolarFire), 10AX057 (Altera Arria 10), 10AX066 (Altera Arria 10).

Which software is used to design with the XC7V585T?

Designs for the XC7V585T are built with AMD Vivado.

Other Virtex-7 devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XC7VX330T	326K 204K LUT6	326K LC	1,120	26.4 Mb	700	28 GTH 13.1 Gb/s	Gen3
XC7VX415T	412K 258K LUT6	412K LC	2,160	30.9 Mb	600	48 GTH 13.1 Gb/s	Gen3
XC7VX485T	486K 304K LUT6	486K LC	2,800	36.2 Mb	700	56 GTX 12.5 Gb/s	Gen2
XC7VX550T	554K 346K LUT6	554K LC	2,880	41.5 Mb	600	80 GTH 13.1 Gb/s	Gen3
XC7VH580T	580K 363K LUT6	580K LC	1,680	33 Mb	600	56 GTH/GTZ 28.05 Gb/s	Gen3
XC7V585T	583K 364K LUT6	583K LC	1,260	27.9 Mb	850	36 GTX 12.5 Gb/s	Gen2
XC7VX690T	693K 433K LUT6	693K LC	3,600	51.7 Mb	1,000	80 GTH 13.1 Gb/s	Gen3
XC7VH870T	876K 548K LUT6	876K LC	2,520	49.6 Mb	300	88 GTH/GTZ 28.05 Gb/s	Gen3
XC7VX980T	979K 612K LUT6	979K LC	3,600	52.7 Mb	900	72 GTH 13.1 Gb/s	Gen3
XC7VX1140T	1139K 712K LUT6	1139K LC	3,360	66.1 Mb	1,100	96 GTH 13.1 Gb/s	Gen3
XC7V2000T	1955K 1222K LUT6	1955K LC	2,160	45.4 Mb	1,200	36 GTX 12.5 Gb/s	Gen2

Source: AMD 7 Series FPGAs Product Selection Guide, XMP101 (v1.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.