FPGA & adaptive SoC databook · online editionRev. 2026.10

Lattice Mach-N2 FPGAs

The Lattice Mach-N2 family has 5 devices, built on the 16 nm process, ranging from 40K LUT4 to 135K LUT4 and from 120 to 520 18×18 multipliers. It uses LUT4 look-up tables. Transceivers: SERDES, up to 16 Gb/s.

DeviceLUTsVendor logicDSPBlock RAMMax I/OTransceiversPCIeCoreScore
Mach-N2 MH0640,000 LUT465K LC1204 Mb1964 SERDES 16 Gb/s——
Mach-N2 MH1061,000 LUT4100K LC2405.5 Mb1964 SERDES 16 Gb/s——
Mach-N2 MH1698,000 LUT4160K LC3608 Mb2484 SERDES 16 Gb/s——
Mach-N2 MH21D132,000 LUT4215K LC52010.4 Mb2364 SERDES 16 Gb/s——
Mach-N2 MH20135,000 LUT4220K LC52012 Mb2484 SERDES 16 Gb/s——

Source: Lattice Mach-N2 product page, Family Table, retrieved 2026-10-26.