Mach-N2 MH10

LatticeMach-N2

The Mach-N2 MH10 is a Mach-N2 FPGA from Lattice, built on a 16 nm process. It provides 61,000 LUT4 look-up tables (100,000 logic cells), 5.5 Mb of block RAM and 240 18×18 multipliers. It offers up to 196 user I/O pins and 4 SERDES transceivers at up to 16 Gb/s. It is available in 2 packages, from the CBG256 (14 × 14 mm) to the CBG484 (18 × 18 mm). Temperature grades: commercial, industrial. Designs are built with Lattice Radiant.

61,000LUTs (LUT4)

24018×18 multipliers

5.5 MbBlock RAM

196Max. user I/O

4Transceivers (16 Gb/s)

Specifications

Vendor	Lattice
Family	Mach-N2
Series	Nexus 2
Process	16 nm
Configuration memory	Internal flash
Look-up tables (LUT4)	61,000
Logic block	4-input look-up table
Logic cells	100,000
Distributed RAM	636 Kb
Block RAM	5.5 Mb (153 × 36 Kb)
DSP (18×18 multiplier)	240

Max. user I/O	196
SERDES transceivers	4 × 16 Gb/s
PCI Express	None
Analog / monitor	None
Design tool	Lattice Radiant

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
CBG256	14 × 14	0.8	141	2
CBG484	18 × 18	0.8	196	4

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	—
Industrial (I)	−40 to 100 °C	—

Alternatives to the Mach-N2 MH10

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
Certus-N2 CT10Lattice Certus-N2	61,000 LUT4	100K LC	240	5.5 Mb	196	4 SERDES 16 Gb/s	—	—
XCAU7PAMD Artix UltraScale+	37,000 LUT6	82K SLC	216	3.8 Mb	248	4 GTH 16.3 Gb/s	Gen3	—
XC7K70TAMD Kintex-7	41,000 LUT6	65.6K LC	240	4.7 Mb	300	8 GTX 12.5 Gb/s	Gen2	—
EP4CGX75Altera Cyclone IV	74,000 LUT4	74K LE	198	4.1 Mb	310	8 XCVR 3.125 Gb/s	Gen2	—
GW5AT-75Gowin Arora V	86,688 LUT4	—	213	4.5 Mb	312	8 SERDES 12.5 Gb/s	Gen3	—
EP2AGX65Altera Arria II	25,300 ALMs	60K LE	312	4.3 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—

Compare side by side: Mach-N2 MH10 vs Certus-N2 CT10, Mach-N2 MH10 vs XCAU7P, Mach-N2 MH10 vs XC7K70T.

Compare the Mach-N2 MH10 with up to three other FPGAs.

Mach-N2 MH10 quick facts

How many LUTs does the Mach-N2 MH10 have?

The Mach-N2 MH10 has 61,000 LUT4 look-up tables (100,000 logic cells as published by Lattice). Logic block: 4-input look-up table.

How many DSP blocks does the Mach-N2 MH10 have?

The Mach-N2 MH10 has 240 18×18 multipliers and 5.5 Mb of block RAM.

Does the Mach-N2 MH10 have transceivers?

Yes, 4 SERDES transceivers at up to 16 Gb/s.

What are the alternatives to the Mach-N2 MH10?

Devices of similar size in other families include Certus-N2 CT10 (Lattice Certus-N2), XCAU7P (AMD Artix UltraScale+), XC7K70T (AMD Kintex-7).

Which software is used to design with the Mach-N2 MH10?

Designs for the Mach-N2 MH10 are built with Lattice Radiant.

Other Mach-N2 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
Mach-N2 MH06	40,000 LUT4	65K LC	120	4 Mb	196	4 SERDES 16 Gb/s	—	—
Mach-N2 MH10	61,000 LUT4	100K LC	240	5.5 Mb	196	4 SERDES 16 Gb/s	—	—
Mach-N2 MH16	98,000 LUT4	160K LC	360	8 Mb	248	4 SERDES 16 Gb/s	—	—
Mach-N2 MH21D	132,000 LUT4	215K LC	520	10.4 Mb	236	4 SERDES 16 Gb/s	—	—
Mach-N2 MH20	135,000 LUT4	220K LC	520	12 Mb	248	4 SERDES 16 Gb/s	—	—

Source: Lattice Mach-N2 product page, Family Table, retrieved 2026-10-26. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.