M2S150
MicrochipSmartFusion2SoCThe M2S150 is a SmartFusion2 SoC FPGA from Microchip, built on a 65 nm process. It provides 146,124 LUT4 look-up tables, 146,124 flip-flops, 4.2 Mb of block RAM and 240 18×18 math blocks (MACC). Its processing system includes a single Arm Cortex-M3 core running at up to 166 MHz. The processing system adds its own MSS with Gigabit Ethernet, high-speed USB, CAN, 2× UART, 2× SPI and 2× I2C. The programmable logic offers up to 574 user I/O pins and 16 SERDES transceivers at up to 5 Gb/s, with hard PCI Express Gen2 blocks. It is available in 3 packages, from the FCSG536 (16 × 16 mm) to the FC1152 (35 × 35 mm). Temperature grades: commercial, industrial, military. Designs are built with Microchip Libero SoC.
Specifications
| Vendor | Microchip |
|---|---|
| Family | SmartFusion2 |
| Series | Flash FPGAs |
| Process | 65 nm |
| Configuration memory | Non-volatile (flash) |
| Look-up tables (LUT4) | 146,124 |
| Logic block | 4-input look-up table |
| LUT note | Logic elements are a 4-input LUT plus a flip-flop (Microchip) |
| Logic elements (LEs) | 146,124 |
| Flip-flops | 146,124 |
| Block RAM | 4.2 Mb (236 × 18 Kb) |
| In-package memory | 512 KB eNVM, 64 KB eSRAM, 240 × 1 Kb uSRAM |
| DSP (18×18 math block (MACC)) | 240 |
| Clock management tiles | 8 |
| Max. user I/O | 574 |
|---|---|
| SERDES transceivers | 16 × 5 Gb/s |
| PCI Express (PL) | 4× Gen2 |
| Hard memory controller | DDR2/DDR3 (2 × 36) |
| Analog / monitor | None |
| Hard processor | 1× Arm Cortex-M3 @ 166 MHz |
| PS connectivity | MSS with Gigabit Ethernet, high-speed USB, CAN, 2× UART, 2× SPI and 2× I2C |
| Design tool | Microchip Libero SoC |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| FCSG536 | 16 × 16 | 0.5 | 293 | 4 |
| FCV484 | 19 × 19 | 0.8 | 248 | 4 |
| FC1152 | 35 × 35 | 1.0 | 574 | 16 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Commercial (C) | 0 to 85 °C | STD, -1 |
| Industrial (I) | −40 to 100 °C | STD, -1 |
| Military (M) | — | STD, -1 |
Alternatives to the M2S150
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| GW5AST-138Gowin Arora V | 138,240 LUT4 | — | 298 | 6 Mb | 376 | 8 SERDES 12.5 Gb/s | Gen3 | — |
| Tz100Efinix Topaz | 108,492 LUT4 | 101K LE | 312 | 6.3 Mb | 223 | 8 SERDES 12.5 Gb/s | Gen3 | — |
| Tz75Efinix Topaz | 80,770 LUT4 | 75.5K LE | 264 | 5.3 Mb | 223 | 8 SERDES 12.5 Gb/s | Gen3 | — |
| Ti85Efinix Titanium | 81,600 LUT4 | 83.2K LE | 300 | 6.2 Mb | 223 | 8 SERDES 16 Gb/s | Gen4 | — |
| A5E 013AAltera Agilex 5 E-Series | 46,800 ALMs | 138K LE | 188 | 7 Mb | 392 | 4 XCVR 28 Gb/s | Gen4 | — |
| A5E 013BAltera Agilex 5 E-Series | 46,800 ALMs | 138K LE | 188 | 7 Mb | 392 | 4 XCVR 17 Gb/s | Gen4 | 298 de25_nano |
Compare side by side: M2S150 vs GW5AST-138, M2S150 vs Tz100, M2S150 vs Tz75.
Compare the M2S150 with up to three other FPGAs.
M2S150 quick facts
How many LUTs does the M2S150 have?
The M2S150 has 146,124 LUT4 look-up tables. Logic block: 4-input look-up table.
How many DSP blocks does the M2S150 have?
The M2S150 has 240 18×18 math blocks (MACC) and 4.2 Mb of block RAM.
Does the M2S150 have transceivers?
Yes, 16 SERDES transceivers at up to 5 Gb/s.
Does the M2S150 have a processor?
Yes. It includes a hard 1× Arm Cortex-M3 processor.
What are the alternatives to the M2S150?
Devices of similar size in other families include GW5AST-138 (Gowin Arora V), Tz100 (Efinix Topaz), Tz75 (Efinix Topaz).
Which software is used to design with the M2S150?
Designs for the M2S150 are built with Microchip Libero SoC.
Other SmartFusion2 devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| M2S005 | 6,060 LUT4 | 6.1K LE | 11 | 0.2 Mb | 209 | — | — | — |
| M2S010 | 12,084 LUT4 | 12.1K LE | 22 | 0.4 Mb | 233 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2S025 | 27,696 LUT4 | 27.7K LE | 34 | 0.5 Mb | 267 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2S050 | 56,340 LUT4 | 56.3K LE | 72 | 1.2 Mb | 377 | 8 SERDES 5 Gb/s | Gen2 | — |
| M2S060 | 56,520 LUT4 | 56.5K LE | 72 | 1.2 Mb | 395 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2S090 | 86,184 LUT4 | 86.2K LE | 84 | 1.9 Mb | 425 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2S150 | 146,124 LUT4 | 146K LE | 240 | 4.2 Mb | 574 | 16 SERDES 5 Gb/s | Gen2 | — |
Source: SmartFusion 2 SoC FPGA Product Brief, DS50003317D. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.