FPGA & adaptive SoC databook · online editionRev. 2026.10

M2S005

MicrochipSmartFusion2SoC

The M2S005 is a SmartFusion2 SoC FPGA from Microchip, built on a 65 nm process. It provides 6,060 LUT4 look-up tables, 6,060 flip-flops, 0.2 Mb of block RAM and 11 18×18 math blocks (MACC). Its processing system includes a single Arm Cortex-M3 core running at up to 166 MHz. The processing system adds its own MSS with Gigabit Ethernet, high-speed USB, CAN, 2× UART, 2× SPI and 2× I2C. The programmable logic offers up to 209 user I/O pins. It is available in 4 packages, from the VFG256 (14 × 14 mm) to the FG484 (23 × 23 mm). Temperature grades: commercial, industrial, automotive. Designs are built with Microchip Libero SoC.

6,060LUTs (LUT4)
1118×18 math blocks (MACC)
0.2 MbBlock RAM
209Max. user I/O
—Transceivers
1× M3Hard processor

Specifications

VendorMicrochip
FamilySmartFusion2
SeriesFlash FPGAs
Process65 nm
Configuration memoryNon-volatile (flash)
Look-up tables (LUT4)6,060
   Logic block4-input look-up table
   LUT noteLogic elements are a 4-input LUT plus a flip-flop (Microchip)
Logic elements (LEs)6,060
Flip-flops6,060
Block RAM0.2 Mb (10 × 18 Kb)
In-package memory128 KB eNVM, 64 KB eSRAM, 11 × 1 Kb uSRAM
DSP (18×18 math block (MACC))11
Clock management tiles2
Max. user I/O209
PL transceiversNone
PCI Express (PL)None
Hard memory controllerDDR2/DDR3 (1 × 18)
Analog / monitorNone
Hard processor1× Arm Cortex-M3 @ 166 MHz
PS connectivityMSS with Gigabit Ethernet, high-speed USB, CAN, 2× UART, 2× SPI and 2× I2C
Design toolMicrochip Libero SoC

Packages

PackageSize (mm)Pitch (mm)User I/OTransceivers
VFG25614 × 140.8161—
VFG40017 × 170.8171—
TQ14420 × 200.584—
FG48423 × 231.0209—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature gradeJunction rangeSpeed grades
Commercial (C)0 to 85 °CSTD, -1
Industrial (I)−40 to 100 °CSTD, -1
Automotive (A)—STD, -1

Alternatives to the M2S005

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

DeviceLUTsVendor logicDSPBlock RAMMax I/OTransceiversPCIeCoreScore
GW1NS-4CGowin LittleBee4,608 LUT4—160.2 Mb106———
GW1NSR-4CGowin LittleBee4,608 LUT4—160.2 Mb106———
GW1NRF-4BGowin LittleBee4,606 LUT4—160.2 Mb25———
M2GL005Microchip IGLOO26,060 LUT46.1K LE110.2 Mb209———
EP4CE6Altera Cyclone IV6,000 LUT46K LE150.3 Mb179———
10CL006Altera Cyclone 10 LP6,000 LUT46K LE150.3 Mb176———

Compare side by side: M2S005 vs GW1NS-4C, M2S005 vs GW1NSR-4C, M2S005 vs GW1NRF-4B.

Compare the M2S005 with up to three other FPGAs.

M2S005 quick facts

How many LUTs does the M2S005 have?

The M2S005 has 6,060 LUT4 look-up tables. Logic block: 4-input look-up table.

How many DSP blocks does the M2S005 have?

The M2S005 has 11 18×18 math blocks (MACC) and 0.2 Mb of block RAM.

Does the M2S005 have transceivers?

No, the M2S005 has no multi-gigabit transceivers. Its user I/O supports up to 209 pins.

Does the M2S005 have a processor?

Yes. It includes a hard 1× Arm Cortex-M3 processor.

What are the alternatives to the M2S005?

Devices of similar size in other families include GW1NS-4C (Gowin LittleBee), GW1NSR-4C (Gowin LittleBee), GW1NRF-4B (Gowin LittleBee).

Which software is used to design with the M2S005?

Designs for the M2S005 are built with Microchip Libero SoC.

Other SmartFusion2 devices

DeviceLUTsVendor logicDSPBlock RAMMax I/OTransceiversPCIeCoreScore
M2S0056,060 LUT46.1K LE110.2 Mb209———
M2S01012,084 LUT412.1K LE220.4 Mb2334 SERDES 5 Gb/sGen2—
M2S02527,696 LUT427.7K LE340.5 Mb2674 SERDES 5 Gb/sGen2—
M2S05056,340 LUT456.3K LE721.2 Mb3778 SERDES 5 Gb/sGen2—
M2S06056,520 LUT456.5K LE721.2 Mb3954 SERDES 5 Gb/sGen2—
M2S09086,184 LUT486.2K LE841.9 Mb4254 SERDES 5 Gb/sGen2—
M2S150146,124 LUT4146K LE2404.2 Mb57416 SERDES 5 Gb/sGen2—

Source: SmartFusion 2 SoC FPGA Product Brief, DS50003317D. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.