5CEA5
AlteraCyclone VSoCThe 5CEA5 is a Cyclone V FPGA from Altera, built on a 28 nm process. It provides 29,080 adaptive logic modules (ALMs) (77,000 logic elements (LEs)), about 58,160 LUT4 equivalents, 116,320 flip-flops, 4.4 Mb of block RAM and 150 variable-precision DSP blocks. It offers up to 240 user I/O pins. It is available in 3 packages, from the M383 (13 × 13 mm) to the F484 (23 × 23 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Cyclone V |
| Series | Cyclone |
| Process | 28 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 58,160 |
| Adaptive logic modules (ALMs) | 29,080 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 77,000 |
| Flip-flops | 116,320 |
| Distributed RAM | 424 Kb |
| Block RAM | 4.4 Mb (446 × 10 Kb) |
| DSP (variable-precision DSP block) | 150 |
| Max. user I/O | 240 |
|---|---|
| Transceivers | None |
| PCI Express | None |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| M383 | 13 × 13 | 0.5 | 175 | — |
| U484 | 19 × 19 | 0.8 | 224 | — |
| F484 | 23 × 23 | 1.0 | 240 | — |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5CEA5
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| T55Efinix Trion | ≈54.2K 54.2K LEs | 54.2K LE | 150 | 2.7 Mb | 278 | — | — |
| Ti60Efinix Titanium | 60.8K 60.8K LUT4 | 62K LE | 160 | 2.6 Mb | 169 | — | — |
| Ti70Efinix Titanium | ≈68.2K 68.2K LEs | 68.2K LE | 160 | 2.6 Mb | 183 | — | — |
| LFE5U-85Lattice ECP5 | 84K 84K LUT4 | — | 156 | 3.7 Mb | 365 | — | — |
| XC7S50AMD Spartan-7 | 52.2K 32.6K LUT6 | 52.2K LC | 120 | 2.6 Mb | 250 | — | — |
| XC7S75AMD Spartan-7 | 76.8K 48K LUT6 | 76.8K LC | 140 | 3.2 Mb | 400 | — | — |
Compare side by side: 5CEA5 vs T55, 5CEA5 vs Ti60, 5CEA5 vs Ti70.
5CEA5 quick facts
How many LUTs does the 5CEA5 have?
The 5CEA5 has 29,080 adaptive logic modules (ALMs), about 58,160 LUT4 equivalents (77,000 logic elements (les) as published by Altera).
How many DSP blocks does the 5CEA5 have?
The 5CEA5 has 150 variable-precision DSP blocks and 4.4 Mb of block RAM.
Does the 5CEA5 have transceivers?
No, the 5CEA5 has no multi-gigabit transceivers. Its user I/O supports up to 240 pins.
What are the alternatives to the 5CEA5?
Devices of similar size in other families include T55 (Efinix Trion), Ti60 (Efinix Titanium), Ti70 (Efinix Titanium).
Which software is used to design with the 5CEA5?
Designs for the 5CEA5 are built with Altera Quartus Prime.
Other Cyclone V devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| 5CEA2 | 18.9K 9.4K ALMs | 25K LE | 25 | 1.7 Mb | 224 | — | — |
| 5CSEA2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | — | — |
| 5CSXC2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGXC3 | 26.9K 13.5K ALMs | 36K LE | 57 | 1.3 Mb | 208 | 3 XCVR 3.125 Gb/s | Gen1 |
| 5CSEA4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | — | — |
| 5CSXC4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA4 | 37K 18.5K ALMs | 49K LE | 66 | 3 Mb | 224 | — | — |
| 5CGXC4 | 37.7K 18.9K ALMs | 50K LE | 70 | 2.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 240 | — | — |
| 5CGXC5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | — | — |
| 5CSXC5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | — | — |
| 5CSXC6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | — | — |
| 5CGXC7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 480 | — | — |
| 5CGXC9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 6.144 Gb/s | Gen2 |
Source: Altera Cyclone V FPGA and SoC FPGA Product Table, 2025.09.24. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.