5CGTD5
AlteraCyclone VSoCThe 5CGTD5 is a Cyclone V FPGA from Altera, built on a 28 nm process. It provides 29,080 adaptive logic modules (ALMs) (77,000 logic elements (LEs)), about 58,160 LUT4 equivalents, 116,320 flip-flops, 4.4 Mb of block RAM and 150 variable-precision DSP blocks. It offers up to 336 user I/O pins and 6 XCVR transceivers at up to 6.144 Gb/s, with hard PCI Express Gen2 blocks. It is available in 5 packages, from the M301 (11 × 11 mm) to the F672 (27 × 27 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Cyclone V |
| Series | Cyclone |
| Process | 28 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 58,160 |
| Adaptive logic modules (ALMs) | 29,080 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 77,000 |
| Flip-flops | 116,320 |
| Distributed RAM | 424 Kb |
| Block RAM | 4.4 Mb (446 × 10 Kb) |
| DSP (variable-precision DSP block) | 150 |
| Max. user I/O | 336 |
|---|---|
| XCVR transceivers | 6 × 6.144 Gb/s |
| PCI Express | 2× Gen2 |
| Analog / monitor | None |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| M301 | 11 × 11 | 0.5 | 129 | 4 |
| M383 | 13 × 13 | 0.5 | 175 | 6 |
| U484 | 19 × 19 | 0.8 | 224 | 6 |
| F484 | 23 × 23 | 1.0 | 240 | 6 |
| F672 | 27 × 27 | 1.0 | 336 | 6 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5CGTD5
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| XCSU65PAMD Spartan UltraScale+ | 48K 30K LUT6 | 66K SLC | 144 | 3.8 Mb | 478 | 4 GTH 16.3 Gb/s | Gen4 |
| XCSU60PAMD Spartan UltraScale+ | 48K 30K LUT6 | 66K SLC | 144 | 3.4 Mb | 262 | 4 GTH 16.3 Gb/s | Gen4 |
| XC7A75TAMD Artix-7 | 75.5K 47.2K LUT6 | 75.5K LC | 180 | 3.7 Mb | 300 | 8 GTP 6.6 Gb/s | Gen2 |
| XCSU100PAMD Spartan UltraScale+ | 73.6K 46K LUT6 | 101K SLC | 144 | 5.1 Mb | 478 | 4 GTH 16.3 Gb/s | Gen4 |
| EP4CGX75Altera Cyclone IV | 74K 74K LUT4 | 74K LE | 198 | 4.1 Mb | 310 | 8 XCVR 3.125 Gb/s | Gen2 |
| LFE5UM-85Lattice ECP5 | 84K 84K LUT4 | — | 156 | 3.7 Mb | 365 | 4 SERDES 3.2 Gb/s | — |
Compare side by side: 5CGTD5 vs XCSU65P, 5CGTD5 vs XCSU60P, 5CGTD5 vs XC7A75T.
5CGTD5 quick facts
How many LUTs does the 5CGTD5 have?
The 5CGTD5 has 29,080 adaptive logic modules (ALMs), about 58,160 LUT4 equivalents (77,000 logic elements (les) as published by Altera).
How many DSP blocks does the 5CGTD5 have?
The 5CGTD5 has 150 variable-precision DSP blocks and 4.4 Mb of block RAM.
Does the 5CGTD5 have transceivers?
Yes, 6 XCVR transceivers at up to 6.144 Gb/s.
What are the alternatives to the 5CGTD5?
Devices of similar size in other families include XCSU65P (AMD Spartan UltraScale+), XCSU60P (AMD Spartan UltraScale+), XC7A75T (AMD Artix-7).
Which software is used to design with the 5CGTD5?
Designs for the 5CGTD5 are built with Altera Quartus Prime.
Other Cyclone V devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| 5CEA2 | 18.9K 9.4K ALMs | 25K LE | 25 | 1.7 Mb | 224 | — | — |
| 5CSEA2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | — | — |
| 5CSXC2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGXC3 | 26.9K 13.5K ALMs | 36K LE | 57 | 1.3 Mb | 208 | 3 XCVR 3.125 Gb/s | Gen1 |
| 5CSEA4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | — | — |
| 5CSXC4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA4 | 37K 18.5K ALMs | 49K LE | 66 | 3 Mb | 224 | — | — |
| 5CGXC4 | 37.7K 18.9K ALMs | 50K LE | 70 | 2.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 240 | — | — |
| 5CGXC5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | — | — |
| 5CSXC5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | — | — |
| 5CSXC6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | — | — |
| 5CGXC7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 480 | — | — |
| 5CGXC9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 6.144 Gb/s | Gen2 |
Source: Altera Cyclone V FPGA and SoC FPGA Product Table, 2025.09.24. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.