5CSXC2
AlteraCyclone VSoCThe 5CSXC2 is a Cyclone V SoC FPGA from Altera, built on a 28 nm process. It provides 9,430 adaptive logic modules (ALMs) (25,000 logic elements (LEs)), about 18,860 LUT4 equivalents, 37,736 flip-flops, 1.4 Mb of block RAM and 36 variable-precision DSP blocks. Its processing system includes two Arm Cortex-A9 cores. The programmable logic offers up to 145 user I/O pins and 6 XCVR transceivers at up to 3.125 Gb/s, with hard PCI Express Gen1 blocks. It comes in a single package, the U672 (23 × 23 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Cyclone V |
| Series | Cyclone |
| Process | 28 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 18,860 |
| Adaptive logic modules (ALMs) | 9,430 |
| LUT note | Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions |
| Logic elements (LEs) | 25,000 |
| Flip-flops | 37,736 |
| Distributed RAM | 138 Kb |
| Block RAM | 1.4 Mb (140 × 10 Kb) |
| DSP (variable-precision DSP block) | 36 |
| Max. user I/O | 145 |
|---|---|
| XCVR transceivers | 6 × 3.125 Gb/s |
| PCI Express (PL) | 2× Gen1 |
| Analog / monitor | None |
| Hard processor | 2× Arm Cortex-A9 |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | PS I/O | Transceivers |
|---|---|---|---|---|---|
| U672 | 23 × 23 | 0.8 | 145 | 181 | 6 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5CSXC2
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| MPFS025TMicrochip PolarFire SoC | 23K 23K LUT4 | 23K LE | 68 | 1.6 Mb | 108 | 4 SERDES 12.5 Gb/s | Gen2 |
| A3C 025Altera Agilex 3 | 17K 8.5K ALMs | 25.1K LE | 34 | 1.3 Mb | 256 | — | — |
| GW5AS-25Gowin Arora V | 23K 23K LUT4 | — | 28 | 1 Mb | 239 | — | — |
| XC7Z007SAMD Zynq 7000 | 23K 14.4K LUT6 | 23K LC | 66 | 1.8 Mb | 100 | — | — |
| A3C 050Altera Agilex 3 | 32K 16K ALMs | 47.2K LE | 65 | 2.4 Mb | 256 | — | — |
| XC7Z010AMD Zynq 7000 | 28.2K 17.6K LUT6 | 28K LC | 80 | 2.1 Mb | 100 | — | — |
Compare side by side: 5CSXC2 vs MPFS025T, 5CSXC2 vs A3C 025, 5CSXC2 vs GW5AS-25.
5CSXC2 quick facts
How many LUTs does the 5CSXC2 have?
The 5CSXC2 has 9,430 adaptive logic modules (ALMs), about 18,860 LUT4 equivalents (25,000 logic elements (les) as published by Altera).
How many DSP blocks does the 5CSXC2 have?
The 5CSXC2 has 36 variable-precision DSP blocks and 1.4 Mb of block RAM.
Does the 5CSXC2 have transceivers?
Yes, 6 XCVR transceivers at up to 3.125 Gb/s.
Does the 5CSXC2 have a processor?
Yes. It includes a hard 2× Arm Cortex-A9 processor.
What are the alternatives to the 5CSXC2?
Devices of similar size in other families include MPFS025T (Microchip PolarFire SoC), A3C 025 (Altera Agilex 3), GW5AS-25 (Gowin Arora V).
Which software is used to design with the 5CSXC2?
Designs for the 5CSXC2 are built with Altera Quartus Prime.
Other Cyclone V devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| 5CEA2 | 18.9K 9.4K ALMs | 25K LE | 25 | 1.7 Mb | 224 | — | — |
| 5CSEA2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | — | — |
| 5CSXC2 | 18.9K 9.4K ALMs | 25K LE | 36 | 1.4 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGXC3 | 26.9K 13.5K ALMs | 36K LE | 57 | 1.3 Mb | 208 | 3 XCVR 3.125 Gb/s | Gen1 |
| 5CSEA4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | — | — |
| 5CSXC4 | 31.8K 15.9K ALMs | 40K LE | 84 | 2.6 Mb | 145 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA4 | 37K 18.5K ALMs | 49K LE | 66 | 3 Mb | 224 | — | — |
| 5CGXC4 | 37.7K 18.9K ALMs | 50K LE | 70 | 2.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CEA5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 240 | — | — |
| 5CGXC5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD5 | 58.2K 29.1K ALMs | 77K LE | 150 | 4.4 Mb | 336 | 6 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | — | — |
| 5CSXC5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD5 | 64.1K 32.1K ALMs | 85K LE | 87 | 3.9 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CSEA6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | — | — |
| 5CSXC6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CSTD6 | 83.8K 41.9K ALMs | 110K LE | 112 | 5.4 Mb | 288 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | — | — |
| 5CGXC7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD7 | 113K 56.5K ALMs | 150K LE | 156 | 6.7 Mb | 480 | 9 XCVR 6.144 Gb/s | Gen2 |
| 5CEA9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 480 | — | — |
| 5CGXC9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 3.125 Gb/s | Gen1 |
| 5CGTD9 | 227K 114K ALMs | 301K LE | 342 | 11.9 Mb | 560 | 12 XCVR 6.144 Gb/s | Gen2 |
Source: Altera Cyclone V FPGA and SoC FPGA Product Table, 2025.09.24. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.