XCAU25P
AMDArtix UltraScale+The XCAU25P is an Artix UltraScale+ FPGA from AMD, built on a 16 nm process. It provides 141,000 LUT6 look-up tables (308,000 system logic cells), about 225,600 LUT4 equivalents, 282,000 flip-flops, 10.5 Mb of block RAM and 1,200 DSP slices. It offers up to 304 user I/O pins and 12 GTY transceivers at up to 32.75 Gb/s, with hard PCI Express Gen3 x8 blocks. It is available in 2 packages, from the SFVB784 (23 × 23 mm) to the FFVB676 (27 × 27 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Artix UltraScale+ |
| Series | UltraScale+ |
| Process | 16 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 225,600 |
| Look-up tables (LUT6) | 141,000 |
| System logic cells | 308,000 |
| Flip-flops | 282,000 |
| Distributed RAM | 4,813 Kb |
| Block RAM | 10.5 Mb (300 × 36 Kb) |
| DSP (DSP slice) | 1,200 |
| Clock management tiles | 4 |
| Max. user I/O | 304 |
|---|---|
| HD I/O | 96 |
| HP I/O | 208 |
| GTY transceivers | 12 × 32.75 Gb/s |
| PCI Express | Gen3 x8 |
| Analog / monitor | System Monitor |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| SFVB784 | 23 × 23 | 0.8 | 304 | 12 |
| FFVB676 | 27 × 27 | 1.0 | 280 | 12 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Extended (E) | 0 to 100 °C | -1, -2 |
| Industrial (I) | −40 to 100 °C | -1, -2, -1L |
Alternatives to the XCAU25P
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| XC7A200TAMD Artix-7 | 215K 135K LUT6 | 215K LC | 740 | 12.8 Mb | 500 | 16 GTP 6.6 Gb/s | Gen2 |
| 10AX027Altera Arria 10 | 203K 102K ALMs | 354K LE | 830 | 14.7 Mb | 384 | 24 XCVR 17.4 Gb/s | Gen3 |
| 10AX032Altera Arria 10 | 237K 119K ALMs | 419K LE | 985 | 17.4 Mb | 384 | 24 XCVR 17.4 Gb/s | Gen3 |
| LAV-AT-G30Lattice Avant-G | 163K 163K LUT4 | 262K LC | 700 | 14.4 Mb | 298 | 12 SERDES 12.5 Gb/s | — |
| LAV-AT-X30Lattice Avant-X | 163K 163K LUT4 | 262K LC | 700 | 14.4 Mb | 298 | 12 SERDES 25 Gb/s | — |
| XC7K325TAMD Kintex-7 | 326K 204K LUT6 | 326K LC | 840 | 15.6 Mb | 500 | 16 GTX 12.5 Gb/s | Gen2 |
Compare side by side: XCAU25P vs XC7A200T, XCAU25P vs 10AX027, XCAU25P vs 10AX032.
XCAU25P quick facts
How many LUTs does the XCAU25P have?
The XCAU25P has 141,000 LUT6 look-up tables, about 225,600 LUT4 equivalents (308,000 system logic cells as published by AMD).
How many DSP blocks does the XCAU25P have?
The XCAU25P has 1,200 DSP slices and 10.5 Mb of block RAM.
Does the XCAU25P have transceivers?
Yes, 12 GTY transceivers at up to 32.75 Gb/s.
What are the alternatives to the XCAU25P?
Devices of similar size in other families include XC7A200T (AMD Artix-7), 10AX027 (Altera Arria 10), 10AX032 (Altera Arria 10).
Which software is used to design with the XCAU25P?
Designs for the XCAU25P are built with AMD Vivado.
Other Artix UltraScale+ devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| XCAU7P | 59.2K 37K LUT6 | 82K SLC | 216 | 3.8 Mb | 248 | 4 GTH 16.3 Gb/s | Gen3 |
| XCAU10P | 70.4K 44K LUT6 | 96K SLC | 400 | 3.5 Mb | 228 | 12 GTH 16.3 Gb/s | Gen4 |
| XCAU15P | 125K 78K LUT6 | 170K SLC | 576 | 5.1 Mb | 228 | 12 GTH 16.3 Gb/s | Gen4 |
| XCAU20P | 174K 109K LUT6 | 238K SLC | 900 | 7 Mb | 228 | 12 GTY 32.75 Gb/s | Gen3 |
| XCAU25P | 226K 141K LUT6 | 308K SLC | 1,200 | 10.5 Mb | 304 | 12 GTY 32.75 Gb/s | Gen3 |
Source: AMD UltraScale+ FPGAs Product Selection Guide, XMP103 (v2.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.