XC2VM3654

AMDVersal Prime Gen 2SoC

The XC2VM3654 is a Versal Prime Gen 2 SoC FPGA from AMD. It provides 318,080 LUT6 look-up tables (695,800 system logic cells), 636,160 flip-flops, 22.2 Mb of block RAM plus 23.3 Mb of UltraRAM and 1,428 DSP Engines. Its processing system includes four Arm Cortex-A78AE cores, a Arm Cortex-R52 real-time processor. The programmable logic offers up to 310 user I/O pins and 24 GTYP transceivers at up to 32.75 Gb/s, with hard PCI Express Gen5 x4 blocks. It is available in 3 packages, from the SFVA1221 ( mm) to the SSVA2112 ( mm). Designs are built with AMD Vivado.

318,080LUTs (LUT6)

1,428DSP Engines

22.2 MbBlock RAM

23.3 MbUltraRAM

310Max. user I/O

24Transceivers (32.75 Gb/s)

4× A78AEHard processor

Specifications

Vendor	AMD
Family	Versal Prime Gen 2
Series	Versal
Configuration memory	SRAM
Look-up tables (LUT6)	318,080
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈508,928
System logic cells	695,800
Flip-flops	636,160
Distributed RAM	9,933 Kb
Block RAM	22.2 Mb
UltraRAM	23.3 Mb
DSP (DSP Engine)	1,428

Max. user I/O	310
GTYP transceivers	24 × 32.75 Gb/s
PCI Express (PL)	2× Gen5 x4
Analog / monitor	System Monitor
Hard processor	4× Arm Cortex-A78AE
Real-time processor	Arm Cortex-R52
Design tool	AMD Vivado

Packages

Package	Pitch (mm)	User I/O	PS I/O	Transceivers
SFVA1221	0.8	224	78	20
SFVK1760	0.8	310	78	32
SSVA2112	0.8	310	78	28

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the XC2VM3654

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
SX 650Altera Stratix 10 GX/SX	207,360 ALMs	612K LE	1,152	49 Mb	392	24 XCVR/XCVR 28.3 Gb/s	Gen3	—
Ti660Efinix Titanium	— 657K LEs, LUTs not published	657K LE	1,260	38.9 Mb	480	24 SERDES 25.8 Gb/s	Gen4	—
A5D 051Altera Agilex 5 D-Series	174,600 ALMs	515K LE	1,472	50.1 Mb	444	24 XCVR 28 Gb/s	Gen4	—
XCZU7CGAMD Zynq UltraScale+ MPSoC	230,000 LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3	—
XCZU7EGAMD Zynq UltraScale+ MPSoC	230,000 LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3	—
XCZU7EVAMD Zynq UltraScale+ MPSoC	230,000 LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3	940 zcu106

Compare side by side: XC2VM3654 vs SX 650, XC2VM3654 vs Ti660, XC2VM3654 vs A5D 051.

Compare the XC2VM3654 with up to three other FPGAs.

XC2VM3654 quick facts

How many LUTs does the XC2VM3654 have?

The XC2VM3654 has 318,080 LUT6 look-up tables (695,800 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XC2VM3654 have?

The XC2VM3654 has 1,428 DSP Engines and 22.2 Mb of block RAM plus 23.3 Mb of UltraRAM.

Does the XC2VM3654 have transceivers?

Yes, 24 GTYP transceivers at up to 32.75 Gb/s.

Does the XC2VM3654 have a processor?

Yes. It includes a hard 4× Arm Cortex-A78AE processor.

What are the alternatives to the XC2VM3654?

Devices of similar size in other families include SX 650 (Altera Stratix 10 GX/SX), Ti660 (Efinix Titanium), A5D 051 (Altera Agilex 5 D-Series).

Which software is used to design with the XC2VM3654?

Designs for the XC2VM3654 are built with AMD Vivado.

Other Versal Prime Gen 2 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC2VM3358	94,592 LUT6	207K SLC	184	5 Mb	308	4 GTYP 32.75 Gb/s	Gen5	—
XC2VM3558	225,000 LUT6	492K SLC	700	13.6 Mb	428	12 GTYP 32.75 Gb/s	Gen5	—
XC2VM3654	318,080 LUT6	696K SLC	1,428	22.2 Mb	310	24 GTYP 32.75 Gb/s	Gen5	—
XC2VM3858	543,104 LUT6	1188K SLC	2,064	47.2 Mb	556	20 GTYP 32.75 Gb/s	Gen5	—

Source: AMD Versal Prime Gen 2 Series Product Selection Guide, XMP506 (v1.3). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.