SX 650

The SX 650 is a Stratix 10 GX/SX SoC FPGA from Altera, built on a 14 nm process. It provides 207,360 adaptive logic modules (ALMs) (612,000 logic elements (LEs)), about 414,720 LUT4 equivalents, 49 Mb of block RAM and 1,152 variable-precision DSP blocks. Its processing system includes four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 392 user I/O pins and 24 XCVR/XCVR transceivers at up to 28.3 Gb/s, with hard PCI Express Gen3 x16 blocks. It comes in a single package, the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.

Specifications

Packages

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the SX 650

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Compare side by side: SX 650 vs A5D 051, SX 650 vs AGF 006, SX 650 vs XCZU7CG, SX 650 vs XCVM1302.

SX 650 quick facts

How many LUTs does the SX 650 have?

The SX 650 has 207,360 adaptive logic modules (ALMs), about 414,720 LUT4 equivalents (612,000 logic elements (les) as published by Altera).

How many DSP blocks does the SX 650 have?

The SX 650 has 1,152 variable-precision DSP blocks and 49 Mb of block RAM.

Does the SX 650 have transceivers?

Yes, 24 XCVR/XCVR transceivers at up to 28.3 Gb/s.

Does the SX 650 have a processor?

Yes. It includes a hard 4× Arm Cortex-A53 processor.

What are the alternatives to the SX 650?

Devices of similar size in other families include A5D 051 (Altera Agilex 5 D-Series), AGF 006 (Altera Agilex 7 F-Series), XCZU7CG (AMD Zynq UltraScale+ MPSoC).

Which software is used to design with the SX 650?

Designs for the SX 650 are built with Altera Quartus Prime.

Other Stratix 10 GX/SX devices

Source: Altera Stratix 10 GX/SX FPGA Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.