LFMXO5-30TD
LatticeMachXO5-NXThe LFMXO5-30TD is a MachXO5-NX FPGA from Lattice, built on a 28 nm process. It provides 25,000 LUT4 look-up tables (30,000 logic cells), 0.8 Mb of block RAM plus 0.5 Mb of LRAM and 48 18×18 multipliers. It offers up to 368 user I/O pins and 1 SERDES transceivers, with hard PCI Express Gen2 blocks. It is available in 3 packages, from the BBG256 (14 × 14 mm) to the BGA484 (19 × 19 mm). Designs are built with Lattice Radiant.
Specifications
| Vendor | Lattice |
|---|---|
| Family | MachXO5-NX |
| Series | Nexus |
| Process | 28 nm |
| Configuration memory | Internal flash |
| LUT4-equivalent capacity | 25,000 |
| Look-up tables (LUT4) | 25,000 |
| LUT note | Derived from logic cells ÷ 1.2 (Lattice definition for Nexus devices) |
| Logic cells | 30,000 |
| Distributed RAM | 190 Kb |
| Block RAM | 0.8 Mb (46 × 18 Kb) |
| LRAM | 0.5 Mb |
| User flash memory | 16,320 Kb |
| DSP (18×18 multiplier) | 48 |
| Max. user I/O | 368 |
|---|---|
| SERDES transceivers | 1 (rate not published) |
| PCI Express | Gen2 |
| Analog / monitor | SAR ADC |
| Design tool | Lattice Radiant |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| BBG256 | 14 × 14 | 0.8 | 170 | 1 |
| BBG400 | 17 × 17 | 0.8 | 315 | — |
| BGA484 | 19 × 19 | 0.8 | 368 | 1 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the LFMXO5-30TD
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| LFD2NX-35Lattice Certus-NX | 29.2K 29.2K LUT4 | 35K LC | 48 | 1.9 Mb | 371 | 1 SERDES 5 Gb/s | Gen2 |
| XCSU35PAMD Spartan UltraScale+ | 25.6K 16K LUT6 | 36K SLC | 48 | 1.7 Mb | 304 | — | — |
| LFD2NX-28Lattice Certus-NX | 23.3K 23.3K LUT4 | 28K LC | 40 | 1 Mb | 191 | 1 SERDES 5 Gb/s | Gen2 |
| GW2A-18Gowin Arora II | 20.7K 20.7K LUT4 | — | 48 | 0.8 Mb | 384 | — | — |
| GW2AR-18Gowin Arora II | 20.7K 20.7K LUT4 | — | 48 | 0.8 Mb | 384 | — | — |
| GW2ANR-18Gowin Arora II | 20.7K 20.7K LUT4 | — | 48 | 0.8 Mb | 384 | — | — |
Compare side by side: LFMXO5-30TD vs LFD2NX-35, LFMXO5-30TD vs XCSU35P, LFMXO5-30TD vs LFD2NX-28.
LFMXO5-30TD quick facts
How many LUTs does the LFMXO5-30TD have?
The LFMXO5-30TD has 25,000 LUT4 look-up tables, about 25,000 LUT4 equivalents (30,000 logic cells as published by Lattice).
How many DSP blocks does the LFMXO5-30TD have?
The LFMXO5-30TD has 48 18×18 multipliers and 0.8 Mb of block RAM plus 0.5 Mb of LRAM.
Does the LFMXO5-30TD have transceivers?
Yes, 1 SERDES transceivers.
What are the alternatives to the LFMXO5-30TD?
Devices of similar size in other families include LFD2NX-35 (Lattice Certus-NX), XCSU35P (AMD Spartan UltraScale+), LFD2NX-28 (Lattice Certus-NX).
Which software is used to design with the LFMXO5-30TD?
Designs for the LFMXO5-30TD are built with Lattice Radiant.
Other MachXO5-NX devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| LFMXO5-15D | 11.7K 11.7K LUT4 | 14K LC | 16 | 0.3 Mb | 305 | — | — |
| LFMXO5-20TD | 16.7K 16.7K LUT4 | 20K LC | 48 | 0.7 Mb | 368 | 1 SERDES | Gen2 |
| LFMXO5-25 | 22.5K 22.5K LUT4 | 27K LC | 20 | 1.4 Mb | 305 | — | — |
| LFMXO5-30TD | 25K 25K LUT4 | 30K LC | 48 | 0.8 Mb | 368 | 1 SERDES | Gen2 |
| LFMXO5-35T | 29.2K 29.2K LUT4 | 35K LC | 48 | 1.9 Mb | 371 | 1 SERDES | Gen2 |
| LFMXO5-55TDQ | 31.7K 31.7K LUT4 | 38K LC | 93 | 0.3 Mb | 297 | 2 SERDES | Gen2 |
| LFMXO5-55T | 44.2K 44.2K LUT4 | 53K LC | 146 | 2.9 Mb | 297 | 2 SERDES | Gen2 |
| LFMXO5-55TD | 44.2K 44.2K LUT4 | 53K LC | 110 | 2.9 Mb | 297 | 2 SERDES | Gen2 |
| LFMXO5-65T | 54.2K 54.2K LUT4 | 65K LC | 128 | 2.2 Mb | 371 | 1 SERDES | Gen2 |
| LFMXO5-100T | 80K 80K LUT4 | 96K LC | 156 | 3.7 Mb | 297 | 2 SERDES | Gen2 |
Source: Lattice MachXO5-NX product page, Family Table, retrieved 2026-10-24. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.