5SGSD5
AlteraStratix VThe 5SGSD5 is a Stratix V FPGA from Altera, built on a 28 nm process. It provides 172,600 adaptive logic modules (ALMs) (457,000 logic elements (LEs)), 690,000 flip-flops, 39.3 Mb of block RAM and 1,590 variable-precision DSP blocks. It offers up to 696 user I/O pins and 36 GX transceivers at up to 14.1 Gb/s, with hard PCI Express Gen3 blocks. It is available in 2 packages, from the F1152 (HF35) (35 × 35 mm) to the F1517 (KF40) (40 × 40 mm). Designs are built with Altera Quartus Prime.
Specifications
| Vendor | Altera |
|---|---|
| Family | Stratix V |
| Series | Stratix |
| Process | 28 nm |
| Configuration memory | SRAM |
| Adaptive logic modules (ALMs) | 172,600 |
| Logic block | adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions) |
| LUT4 equivalent (approx.) | ≈345,200 |
| Logic elements (LEs) | 457,000 |
| Flip-flops | 690,000 |
| Block RAM | 39.3 Mb (2014 × 20 Kb) |
| DSP (variable-precision DSP block) | 1,590 |
| Clock management tiles | 24 |
| Max. user I/O | 696 |
|---|---|
| GX transceivers | 36 × 14.1 Gb/s |
| PCI Express | Gen3 |
| Analog / monitor | None |
| CoreScore | 1,152 SERV cores (storeypeak) |
| Design tool | Altera Quartus Prime |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| F1152 (HF35) | 35 × 35 | 1.0 | 552 | 24 |
| F1517 (KF40) | 40 × 40 | 1.0 | 696 | 36 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Alternatives to the 5SGSD5
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| LAV-AT-G70Lattice Avant-G | 397,000 LUT4 | 637K LC | 1,800 | 35.6 Mb | 554 | 28 SERDES 12.5 Gb/s | — | — |
| LAV-AT-X70Lattice Avant-X | 397,000 LUT4 | 637K LC | 1,800 | 35.6 Mb | 554 | 28 SERDES 25 Gb/s | — | — |
| 10AX057Altera Arria 10 | 217,080 ALMs | 747K LE | 1,523 | 35.2 Mb | 696 | 48 XCVR 17.4 Gb/s | Gen3 | — |
| XC2KU050PAMD Kintex UltraScale+ Gen 2 | 225,000 LUT6 | 491K SLC | 1,872 | 17.7 Mb | 516 | 24 GTY 32.75 Gb/s | Gen4 | — |
| 10AX066Altera Arria 10 | 250,540 ALMs | 865K LE | 1,687 | 41.7 Mb | 696 | 48 XCVR 17.4 Gb/s | Gen3 | — |
| 10AX048Altera Arria 10 | 181,790 ALMs | 629K LE | 1,368 | 28.1 Mb | 492 | 36 XCVR 17.4 Gb/s | Gen3 | — |
Compare side by side: 5SGSD5 vs LAV-AT-G70, 5SGSD5 vs LAV-AT-X70, 5SGSD5 vs 10AX057, 5SGSD5 vs XC2KU050P.
Compare the 5SGSD5 with up to three other FPGAs.
5SGSD5 quick facts
How many LUTs does the 5SGSD5 have?
The 5SGSD5 has 172,600 adaptive logic modules (ALMs) (457,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).
How many DSP blocks does the 5SGSD5 have?
The 5SGSD5 has 1,590 variable-precision DSP blocks and 39.3 Mb of block RAM.
Does the 5SGSD5 have transceivers?
Yes, 36 GX transceivers at up to 14.1 Gb/s.
What is the CoreScore of the 5SGSD5?
The 5SGSD5 fits 1,152 SERV RISC-V cores in the CoreScore benchmark (board: storeypeak). CoreScore counts how many of these bit-serial cores the device and its tools can place and route, a practical measure of usable logic.
What are the alternatives to the 5SGSD5?
Devices of similar size in other families include LAV-AT-G70 (Lattice Avant-G), LAV-AT-X70 (Lattice Avant-X), 10AX057 (Altera Arria 10).
Which software is used to design with the 5SGSD5?
Designs for the 5SGSD5 are built with Altera Quartus Prime.
Other Stratix V devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| 5SGSD3 | 89,000 ALMs | 236K LE | 600 | 13.4 Mb | 432 | 24 GX 14.1 Gb/s | Gen3 | — |
| 5SGXA3 | 128,300 ALMs | 340K LE | 256 | 18.7 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | — |
| 5SGSD4 | 135,840 ALMs | 360K LE | 1,044 | 18.7 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | — |
| 5SGXA4 | 158,500 ALMs | 420K LE | 256 | 37.1 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | — |
| 5SGTC5 | 160,400 ALMs | 425K LE | 256 | 45 Mb | 600 | 36 GT/GX 28.05 Gb/s | Gen3 | — |
| 5SGSD5 | 172,600 ALMs | 457K LE | 1,590 | 39.3 Mb | 696 | 36 GX 14.1 Gb/s | Gen3 | 1,152 storeypeak |
| 5SGXA5 | 185,000 ALMs | 490K LE | 256 | 45 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | — |
| 5SGXB5 | 185,000 ALMs | 490K LE | 399 | 41 Mb | 600 | 66 GX 14.1 Gb/s | Gen3 | — |
| 5SGSD6 | 220,000 ALMs | 583K LE | 1,775 | 45.3 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | — |
| 5SGXB6 | 225,400 ALMs | 597K LE | 399 | 52 Mb | 600 | 66 GX 14.1 Gb/s | Gen3 | — |
| 5SGTC7 | 234,720 ALMs | 622K LE | 256 | 50 Mb | 600 | 36 GT/GX 28.05 Gb/s | Gen3 | — |
| 5SGXA7 | 234,720 ALMs | 622K LE | 256 | 50 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | 1,568 de5_net |
| 5SGSD8 | 262,400 ALMs | 695K LE | 1,963 | 50.1 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | — |
| 5SGXA9 | 317,000 ALMs | 840K LE | 352 | 51.6 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | — |
| 5SGXB9 | 317,000 ALMs | 840K LE | 352 | 51.6 Mb | 600 | 66 GX 14.1 Gb/s | Gen3 | — |
| 5SEE9 | 317,000 ALMs | 840K LE | 352 | 51.6 Mb | 840 | — | — | — |
| 5SGXAB | 359,200 ALMs | 952K LE | 352 | 51.6 Mb | 840 | 48 GX 14.1 Gb/s | Gen3 | — |
| 5SGXBB | 359,200 ALMs | 952K LE | 352 | 51.6 Mb | 600 | 66 GX 14.1 Gb/s | Gen3 | — |
| 5SEEB | 359,200 ALMs | 952K LE | 352 | 51.6 Mb | 840 | — | — | — |
Source: Stratix V Device Overview, 683258 (2024.12.20). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet. CoreScore result from the CoreScore world ranking (olofk/corescore).