XCVU065

AMDVirtex UltraScale

The XCVU065 is a Virtex UltraScale FPGA from AMD, built on a 20 nm process. It provides 358,080 LUT6 look-up tables (783,000 system logic cells), 716,160 flip-flops, 44.3 Mb of block RAM and 600 DSP slices. It offers up to 520 user I/O pins and 40 GTH/GTY transceivers at up to 30.5 Gb/s, with hard PCI Express Gen3 blocks. It comes in a single package, the C1517 (40 × 40 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.

358,080LUTs (LUT6)

600DSP slices

44.3 MbBlock RAM

520Max. user I/O

40Transceivers (30.5 Gb/s)

Specifications

Vendor	AMD
Family	Virtex UltraScale
Series	UltraScale
Process	20 nm
Configuration memory	SRAM
Look-up tables (LUT6)	358,080
Logic block	6-input look-up table, fracturable into two LUT5 with shared inputs
LUT4 equivalent (approx.)	≈572,928
System logic cells	783,000
Flip-flops	716,160
Distributed RAM	4,830 Kb
Block RAM	44.3 Mb (1260 × 36 Kb)
DSP (DSP slice)	600
Clock management tiles	10

Max. user I/O	520
HP I/O	468
Differential pairs	240
GTH transceivers	20 × 16.3 Gb/s
GTY transceivers	20 × 30.5 Gb/s
PCI Express	2× Gen3
150G Interlaken	3
100G Ethernet MAC	3
Analog / monitor	System Monitor
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
C1517	40 × 40	1.0	520	40

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Extended (E)	0 to 100 °C	-1H, -2, -3
Industrial (I)	−40 to 100 °C	-1, -2

Alternatives to the XCVU065

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
5SGXB6Altera Stratix V	225,400 ALMs	597K LE	399	52 Mb	600	66 GX 14.1 Gb/s	Gen3	—
5SGXA9Altera Stratix V	317,000 ALMs	840K LE	352	51.6 Mb	840	48 GX 14.1 Gb/s	Gen3	—
5SGXB9Altera Stratix V	317,000 ALMs	840K LE	352	51.6 Mb	600	66 GX 14.1 Gb/s	Gen3	—
XCKU095AMD Kintex UltraScale	537,600 LUT6	1176K SLC	768	59.1 Mb	702	64 GTH/GTY 16.3 Gb/s	Gen3	—
5SGXABAltera Stratix V	359,200 ALMs	952K LE	352	51.6 Mb	840	48 GX 14.1 Gb/s	Gen3	—
5SGXBBAltera Stratix V	359,200 ALMs	952K LE	352	51.6 Mb	600	66 GX 14.1 Gb/s	Gen3	—

Compare side by side: XCVU065 vs 5SGXB6, XCVU065 vs 5SGXA9, XCVU065 vs 5SGXB9, XCVU065 vs XCKU095, XCVU065 vs 5SGXAB, XCVU065 vs 5SGXBB.

Compare the XCVU065 with up to three other FPGAs.

XCVU065 quick facts

How many LUTs does the XCVU065 have?

The XCVU065 has 358,080 LUT6 look-up tables (783,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.

How many DSP blocks does the XCVU065 have?

The XCVU065 has 600 DSP slices and 44.3 Mb of block RAM.

Does the XCVU065 have transceivers?

Yes, 40 GTH/GTY transceivers at up to 30.5 Gb/s.

What are the alternatives to the XCVU065?

Devices of similar size in other families include 5SGXB6 (Altera Stratix V), 5SGXA9 (Altera Stratix V), 5SGXB9 (Altera Stratix V).

Which software is used to design with the XCVU065?

Designs for the XCVU065 are built with AMD Vivado.

Other Virtex UltraScale devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XCVU065	358,080 LUT6	783K SLC	600	44.3 Mb	520	40 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU080	445,712 LUT6	975K SLC	672	50 Mb	832	64 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU095	537,600 LUT6	1176K SLC	768	60.8 Mb	832	64 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU125	716,160 LUT6	1567K SLC	1,200	88.6 Mb	832	80 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU160	926,400 LUT6	2027K SLC	1,560	115.2 Mb	702	104 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU190	1,074,240 LUT6	2350K SLC	1,800	132.9 Mb	702	120 GTH/GTY 30.5 Gb/s	Gen3	—
XCVU440	2,532,960 LUT6	5541K SLC	2,880	88.6 Mb	1,456	48 GTH 16.3 Gb/s	Gen3	—

Source: AMD UltraScale FPGAs Product Selection Guide, XMP102 (v1.7). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.