XCVU125
AMDVirtex UltraScaleThe XCVU125 is a Virtex UltraScale FPGA from AMD, built on a 20 nm process. It provides 716,160 LUT6 look-up tables (1,567,000 system logic cells), 1,432,320 flip-flops, 88.6 Mb of block RAM and 1,200 DSP slices. It offers up to 832 user I/O pins and 80 GTH/GTY transceivers at up to 30.5 Gb/s, with hard PCI Express Gen3 blocks. It is available in 5 packages, from the D1517 (40 × 40 mm) to the C2104 (47.5 × 47.5 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Virtex UltraScale |
| Series | UltraScale |
| Process | 20 nm |
| Configuration memory | SRAM |
| Look-up tables (LUT6) | 716,160 |
| Logic block | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈1,145,856 |
| System logic cells | 1,567,000 |
| Flip-flops | 1,432,320 |
| Distributed RAM | 9,660 Kb |
| Block RAM | 88.6 Mb (2520 × 36 Kb) |
| DSP (DSP slice) | 1,200 |
| Clock management tiles | 20 |
| Max. user I/O | 832 |
|---|---|
| HP I/O | 780 |
| Differential pairs | 384 |
| GTH transceivers | 40 × 16.3 Gb/s |
| GTY transceivers | 40 × 30.5 Gb/s |
| PCI Express | 4× Gen3 |
| 150G Interlaken | 6 |
| 100G Ethernet MAC | 6 |
| Analog / monitor | System Monitor |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| D1517 | 40 × 40 | 1.0 | 338 | 72 |
| B1760 | 42.5 × 42.5 | 1.0 | 702 | 52 |
| A2104 | 47.5 × 47.5 | 1.0 | 832 | 52 |
| B2104 | 47.5 × 47.5 | 1.0 | 702 | 76 |
| C2104 | 47.5 × 47.5 | 1.0 | 416 | 80 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Extended (E) | 0 to 100 °C | -1H, -2, -3 |
| Industrial (I) | −40 to 100 °C | -1, -2 |
Alternatives to the XCVU125
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCKU15PAMD Kintex UltraScale+ | 523,000 LUT6 | 1143K SLC | 1,968 | 34.6 Mb | 668 | 76 GTH/GTY 32.75 Gb/s | Gen3 | — |
| 10AX115Altera Arria 10 | 427,200 ALMs | 1506K LE | 1,518 | 53 Mb | 768 | 96 XCVR 17.4 Gb/s | Gen3 | 2,600 intel_a10gx_devkit |
| 10AT115Altera Arria 10 | 427,200 ALMs | 1506K LE | 1,518 | 53 Mb | 624 | 78 XCVR/XCVR 25.78 Gb/s | Gen3 | — |
| XCKU095AMD Kintex UltraScale | 537,600 LUT6 | 1176K SLC | 768 | 59.1 Mb | 702 | 64 GTH/GTY 16.3 Gb/s | Gen3 | — |
| XCKU19PAMD Kintex UltraScale+ | 842,000 LUT6 | 1843K SLC | 1,080 | 60.8 Mb | 540 | 32 GTY 32.75 Gb/s | Gen3 | — |
| 10AX090Altera Arria 10 | 339,620 ALMs | 1180K LE | 1,518 | 47.3 Mb | 768 | 96 XCVR 17.4 Gb/s | Gen3 | — |
Compare side by side: XCVU125 vs XCKU15P, XCVU125 vs 10AX115, XCVU125 vs 10AT115, XCVU125 vs XCKU19P.
Compare the XCVU125 with up to three other FPGAs.
XCVU125 quick facts
How many LUTs does the XCVU125 have?
The XCVU125 has 716,160 LUT6 look-up tables (1,567,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.
How many DSP blocks does the XCVU125 have?
The XCVU125 has 1,200 DSP slices and 88.6 Mb of block RAM.
Does the XCVU125 have transceivers?
Yes, 80 GTH/GTY transceivers at up to 30.5 Gb/s.
What are the alternatives to the XCVU125?
Devices of similar size in other families include XCKU15P (AMD Kintex UltraScale+), 10AX115 (Altera Arria 10), 10AT115 (Altera Arria 10).
Which software is used to design with the XCVU125?
Designs for the XCVU125 are built with AMD Vivado.
Other Virtex UltraScale devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCVU065 | 358,080 LUT6 | 783K SLC | 600 | 44.3 Mb | 520 | 40 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU080 | 445,712 LUT6 | 975K SLC | 672 | 50 Mb | 832 | 64 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU095 | 537,600 LUT6 | 1176K SLC | 768 | 60.8 Mb | 832 | 64 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU125 | 716,160 LUT6 | 1567K SLC | 1,200 | 88.6 Mb | 832 | 80 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU160 | 926,400 LUT6 | 2027K SLC | 1,560 | 115.2 Mb | 702 | 104 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU190 | 1,074,240 LUT6 | 2350K SLC | 1,800 | 132.9 Mb | 702 | 120 GTH/GTY 30.5 Gb/s | Gen3 | — |
| XCVU440 | 2,532,960 LUT6 | 5541K SLC | 2,880 | 88.6 Mb | 1,456 | 48 GTH 16.3 Gb/s | Gen3 | — |
Source: AMD UltraScale FPGAs Product Selection Guide, XMP102 (v1.7). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.