XCZU2CG

AMDZynq UltraScale+ MPSoCSoC

The XCZU2CG is a Zynq UltraScale+ MPSoC FPGA from AMD, built on a 16 nm process. It provides 47,000 LUT6 look-up tables (103,000 system logic cells), about 75,200 LUT4 equivalents, 94,000 flip-flops, 5.3 Mb of block RAM and 240 DSP slices. Its processing system includes two Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The processing system adds its own PCIe Gen2 x4, 2x USB 3.0, SATA 3.1, DisplayPort, 4x Gigabit Ethernet, with 4 PS-GTR transceivers at 6 Gb/s. The programmable logic offers up to 252 user I/O pins. It is available in 4 packages, from the A530 (9.5 × 16 mm) to the C784 (23 × 23 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.

75.2KLUT4-equivalent

47KLUTs (LUT6)

240DSP slices

5.3 MbBlock RAM

252Max. user I/O

—Transceivers

2× A53Hard processor

Specifications

Vendor	AMD
Family	Zynq UltraScale+ MPSoC
Series	UltraScale+
Process	16 nm
Configuration memory	SRAM
LUT4-equivalent capacity	75,200
Look-up tables (LUT6)	47,000
System logic cells	103,000
Flip-flops	94,000
Distributed RAM	1,229 Kb
Block RAM	5.3 Mb
DSP (DSP slice)	240
Clock management tiles	3

Max. user I/O	252
PL transceivers	None
PCI Express (PL)	None
Analog / monitor	System Monitor
Hard processor	2× Arm Cortex-A53 @ 1.3 GHz
PS-GTR transceivers	4 × 6 Gb/s
PS connectivity	PCIe Gen2 x4, 2x USB 3.0, SATA 3.1, DisplayPort, 4x Gigabit Ethernet
Real-time processor	Dual Arm Cortex-R5F
Design tool	AMD Vivado

Packages

Package	Size (mm)	User I/O	PS I/O	Transceivers
A530	9.5 × 16	82	170	—
A484	19 × 19	82	170	—
A625	21 × 21	180	170	—
C784	23 × 23	252	214	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Extended (E)	0 to 100 °C	-1, -2, -2L
Industrial (I)	−40 to 100 °C	-1, -1L, -2

Alternatives to the XCZU2CG

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XC7Z020AMD Zynq 7000	85.1K 53.2K LUT6	85K LC	220	4.9 Mb	200	—	—
XC7Z014SAMD Zynq 7000	65K 40.6K LUT6	65K LC	170	3.8 Mb	200	—	—
GW5AS-138Gowin Arora V	138K 138K LUT4	—	298	6 Mb	312	—	—
5CSEA6Altera Cyclone V	83.8K 41.9K ALMs	110K LE	112	5.4 Mb	288	—	—
XCVE2102AMD Versal AI Edge	58.6K 36.6K LUT6	80.1K SLC	176	1.7 Mb	216	—	—
MPFS095TMicrochip PolarFire SoC	93K 93K LUT4	93K LE	292	6 Mb	276	4 SERDES 12.5 Gb/s	Gen2

Compare side by side: XCZU2CG vs XC7Z020, XCZU2CG vs XC7Z014S, XCZU2CG vs GW5AS-138, XCZU2CG vs XCVE2102.

XCZU2CG quick facts

How many LUTs does the XCZU2CG have?

The XCZU2CG has 47,000 LUT6 look-up tables, about 75,200 LUT4 equivalents (103,000 system logic cells as published by AMD).

How many DSP blocks does the XCZU2CG have?

The XCZU2CG has 240 DSP slices and 5.3 Mb of block RAM.

Does the XCZU2CG have transceivers?

No, the XCZU2CG has no multi-gigabit transceivers. Its user I/O supports up to 252 pins.

Does the XCZU2CG have a processor?

Yes. It includes a hard 2× Arm Cortex-A53 processor.

What are the alternatives to the XCZU2CG?

Devices of similar size in other families include XC7Z020 (AMD Zynq 7000), XC7Z014S (AMD Zynq 7000), GW5AS-138 (Gowin Arora V).

Which software is used to design with the XCZU2CG?

Designs for the XCZU2CG are built with AMD Vivado.

Other Zynq UltraScale+ MPSoC devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XCZU1CG	59.2K 37K LUT6	81K SLC	216	3.8 Mb	180	—	—
XCZU1EG	59.2K 37K LUT6	81K SLC	216	3.8 Mb	180	—	—
XCZU2CG	75.2K 47K LUT6	103K SLC	240	5.3 Mb	252	—	—
XCZU2EG	75.2K 47K LUT6	103K SLC	240	5.3 Mb	252	—	—
XCZU3CG	114K 71K LUT6	154K SLC	360	7.6 Mb	252	—	—
XCZU3EG	114K 71K LUT6	154K SLC	360	7.6 Mb	252	—	—
XCZU3TCG	115K 72K LUT6	157K SLC	576	5.1 Mb	124	8 GTH 16.3 Gb/s	Gen3
XCZU3TEG	115K 72K LUT6	157K SLC	576	5.1 Mb	124	8 GTH 16.3 Gb/s	Gen3
XCZU4CG	141K 88K LUT6	192K SLC	728	4.5 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU4EG	141K 88K LUT6	192K SLC	728	4.5 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU4EV	141K 88K LUT6	192K SLC	728	4.5 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU5CG	187K 117K LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU5EG	187K 117K LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU5EV	187K 117K LUT6	256K SLC	1,248	5.1 Mb	252	16 GTH 16.3 Gb/s	Gen3
XCZU6CG	344K 215K LUT6	469K SLC	1,973	25.1 Mb	328	24 GTH 16.3 Gb/s	—
XCZU6EG	344K 215K LUT6	469K SLC	1,973	25.1 Mb	328	24 GTH 16.3 Gb/s	—
XCZU7CG	368K 230K LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3
XCZU7EG	368K 230K LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3
XCZU7EV	368K 230K LUT6	504K SLC	1,728	11 Mb	464	24 GTH 16.3 Gb/s	Gen3
XCZU9CG	438K 274K LUT6	600K SLC	2,520	32.1 Mb	328	24 GTH 16.3 Gb/s	—
XCZU9EG	438K 274K LUT6	600K SLC	2,520	32.1 Mb	328	24 GTH 16.3 Gb/s	—
XCZU11EG	478K 299K LUT6	653K SLC	2,928	21.1 Mb	512	48 GTH/GTY 32.75 Gb/s	Gen3
XCZU15EG	546K 341K LUT6	747K SLC	3,528	26.2 Mb	328	24 GTH 16.3 Gb/s	—
XCZU17EG	677K 423K LUT6	926K SLC	1,590	28 Mb	668	72 GTH/GTY 32.75 Gb/s	Gen3
XCZU19EG	837K 523K LUT6	1143K SLC	1,968	34.6 Mb	668	72 GTH/GTY 32.75 Gb/s	Gen3

Source: AMD Zynq UltraScale+ MPSoC Product Selection Guide, XMP104 (v2.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.