Microchip IGLOO2 FPGAs
The Microchip IGLOO2 family has 7 devices, built on the 65 nm process, ranging from 6.1K LUT4 to 146K LUT4 and from 11 to 240 18×18 math blocks (MACC). It uses LUT4 look-up tables. Transceivers: SERDES, up to 5 Gb/s.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| M2GL005 | 6,060 LUT4 | 6.1K LE | 11 | 0.2 Mb | 209 | — | — | — |
| M2GL010 | 12,084 LUT4 | 12.1K LE | 22 | 0.4 Mb | 233 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2GL025 | 27,696 LUT4 | 27.7K LE | 34 | 0.5 Mb | 267 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2GL050 | 56,340 LUT4 | 56.3K LE | 72 | 1.2 Mb | 377 | 8 SERDES 5 Gb/s | Gen2 | — |
| M2GL060 | 56,520 LUT4 | 56.5K LE | 72 | 1.2 Mb | 387 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2GL090 | 86,184 LUT4 | 86.2K LE | 84 | 1.9 Mb | 425 | 4 SERDES 5 Gb/s | Gen2 | — |
| M2GL150 | 146,124 LUT4 | 146K LE | 240 | 4.2 Mb | 574 | 16 SERDES 5 Gb/s | Gen2 | — |
Source: IGLOO2 FPGA Product Brief, PB0121 rev. 15.0.