M2GL050

MicrochipIGLOO2

The M2GL050 is an IGLOO2 FPGA from Microchip, built on a 65 nm process. It provides 56,340 LUT4 look-up tables, 56,340 flip-flops, 1.2 Mb of block RAM and 72 18×18 math blocks (MACC). It offers up to 377 user I/O pins and 8 SERDES transceivers at up to 5 Gb/s, with hard PCI Express Gen2 blocks. It is available in 4 packages, from the FCS325 (11 × 11 mm) to the FG896 (31 × 31 mm). Temperature grades: commercial, industrial, military, automotive. Designs are built with Microchip Libero SoC.

56,340LUTs (LUT4)

7218×18 math blocks (MACC)

1.2 MbBlock RAM

377Max. user I/O

8Transceivers (5 Gb/s)

Specifications

Vendor	Microchip
Family	IGLOO2
Series	Flash FPGAs
Process	65 nm
Configuration memory	Non-volatile (flash)
Look-up tables (LUT4)	56,340
Logic block	4-input look-up table
LUT note	Logic elements are a 4-input LUT plus a flip-flop (Microchip)
Logic elements (LEs)	56,340
Flip-flops	56,340
Block RAM	1.2 Mb (69 × 18 Kb)
In-package memory	256 KB eNVM, 64 KB eSRAM, 72 × 1 Kb uSRAM
DSP (18×18 math block (MACC))	72
Clock management tiles	6

Max. user I/O	377
SERDES transceivers	8 × 5 Gb/s
PCI Express	2× Gen2
Hard memory controller	DDR2/DDR3 (2 × 36)
Analog / monitor	None
Design tool	Microchip Libero SoC

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
FCS325	11 × 11	0.5	200	2
VF400	17 × 17	0.8	207	4
FG484	23 × 23	1.0	267	4
FG896	31 × 31	1.0	377	8

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Commercial (C)	0 to 85 °C	STD, -1
Industrial (I)	−40 to 100 °C	STD, -1
Military (M)	—	STD, -1
Automotive (A)	—	STD, -1

Alternatives to the M2GL050

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
LFE5UM-45Lattice ECP5	44,000 LUT4	—	72	1.9 Mb	245	4 SERDES 3.2 Gb/s	—	—
LFE5UM5G-45Lattice ECP5	44,000 LUT4	—	72	1.9 Mb	245	4 SERDES 5 Gb/s	—	—
5CGXC4Altera Cyclone V	18,868 ALMs	50K LE	70	2.4 Mb	336	6 XCVR 3.125 Gb/s	Gen1	—
GW5AT-60Gowin Arora V	59,904 LUT4	—	118	2.1 Mb	320	4 SERDES 12.5 Gb/s	Gen3	—
XC7A35TAMD Artix-7	20,800 LUT6	33.3K LC	90	1.8 Mb	250	4 GTP 6.6 Gb/s	Gen2	104 arty_a7_35t
EP4CGX30Altera Cyclone IV	29,000 LUT4	29K LE	80	1.1 Mb	290	4 XCVR 3.125 Gb/s	Gen2	—

Compare side by side: M2GL050 vs LFE5UM-45, M2GL050 vs LFE5UM5G-45, M2GL050 vs 5CGXC4.

Compare the M2GL050 with up to three other FPGAs.

M2GL050 quick facts

How many LUTs does the M2GL050 have?

The M2GL050 has 56,340 LUT4 look-up tables. Logic block: 4-input look-up table.

How many DSP blocks does the M2GL050 have?

The M2GL050 has 72 18×18 math blocks (MACC) and 1.2 Mb of block RAM.

Does the M2GL050 have transceivers?

Yes, 8 SERDES transceivers at up to 5 Gb/s.

What are the alternatives to the M2GL050?

Devices of similar size in other families include LFE5UM-45 (Lattice ECP5), LFE5UM5G-45 (Lattice ECP5), 5CGXC4 (Altera Cyclone V).

Which software is used to design with the M2GL050?

Designs for the M2GL050 are built with Microchip Libero SoC.

Other IGLOO2 devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
M2GL005	6,060 LUT4	6.1K LE	11	0.2 Mb	209	—	—	—
M2GL010	12,084 LUT4	12.1K LE	22	0.4 Mb	233	4 SERDES 5 Gb/s	Gen2	—
M2GL025	27,696 LUT4	27.7K LE	34	0.5 Mb	267	4 SERDES 5 Gb/s	Gen2	—
M2GL050	56,340 LUT4	56.3K LE	72	1.2 Mb	377	8 SERDES 5 Gb/s	Gen2	—
M2GL060	56,520 LUT4	56.5K LE	72	1.2 Mb	387	4 SERDES 5 Gb/s	Gen2	—
M2GL090	86,184 LUT4	86.2K LE	84	1.9 Mb	425	4 SERDES 5 Gb/s	Gen2	—
M2GL150	146,124 LUT4	146K LE	240	4.2 Mb	574	16 SERDES 5 Gb/s	Gen2	—

Source: IGLOO2 FPGA Product Brief, PB0121 rev. 15.0. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.