EP2AGX125

AlteraArria II

The EP2AGX125 is an Arria II FPGA from Altera, built on a 40 nm process. It provides 49,640 adaptive logic modules (ALMs) (118,000 logic elements (LEs)), 99,280 flip-flops, 6.4 Mb of block RAM and 576 18×18 multipliers. It offers up to 452 user I/O pins and 12 XCVR transceivers at up to 6.375 Gb/s, with hard PCI Express Gen1 blocks. It is available in 3 packages, from the F572 (25 × 25 mm) to the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.

49,640ALMs

57618×18 multipliers

6.4 MbBlock RAM

452Max. user I/O

12Transceivers (6.375 Gb/s)

Specifications

Vendor	Altera
Family	Arria II
Series	Arria
Process	40 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	49,640
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈99,280
Logic elements (LEs)	118,000
Flip-flops	99,280
Distributed RAM	1,551 Kb
Block RAM	6.4 Mb (730 × 9 Kb)
DSP (18×18 multiplier)	576
Clock management tiles	6

Max. user I/O	452
XCVR transceivers	12 × 6.375 Gb/s
PCI Express	Gen1
Analog / monitor	None
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F572	25 × 25	1.0	260	8
F780	29 × 29	1.0	372	12
F1152	35 × 35	1.0	452	12

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the EP2AGX125

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
EP4SGX110Altera Stratix IV	42,240 ALMs	106K LE	512	8.1 Mb	480	24 XCVR/XCVR 8.5 Gb/s	Gen2	—
XCAU15PAMD Artix UltraScale+	78,000 LUT6	170K SLC	576	5.1 Mb	228	12 GTH 16.3 Gb/s	Gen4	—
XC6VLX130TAMD Virtex-6	80,000 LUT6	128K LC	480	9.3 Mb	600	20 GTX 6.6 Gb/s	Gen2	—
Certus-N2 CT16Lattice Certus-N2	98,000 LUT4	160K LC	360	8 Mb	298	8 SERDES 16 Gb/s	—	—
5AGXA3Altera Arria V	58,900 ALMs	156K LE	396	10.3 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
XCSU150PAMD Spartan UltraScale+	63,000 LUT6	138K SLC	384	5.9 Mb	572	8 GTH 16.3 Gb/s	Gen4	—

Compare side by side: EP2AGX125 vs EP4SGX110, EP2AGX125 vs XCAU15P, EP2AGX125 vs XC6VLX130T.

Compare the EP2AGX125 with up to three other FPGAs.

EP2AGX125 quick facts

How many LUTs does the EP2AGX125 have?

The EP2AGX125 has 49,640 adaptive logic modules (ALMs) (118,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the EP2AGX125 have?

The EP2AGX125 has 576 18×18 multipliers and 6.4 Mb of block RAM.

Does the EP2AGX125 have transceivers?

Yes, 12 XCVR transceivers at up to 6.375 Gb/s.

What are the alternatives to the EP2AGX125?

Devices of similar size in other families include EP4SGX110 (Altera Stratix IV), XCAU15P (AMD Artix UltraScale+), XC6VLX130T (AMD Virtex-6).

Which software is used to design with the EP2AGX125?

Designs for the EP2AGX125 are built with Altera Quartus Prime.

Other Arria II devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
EP2AGX45	18,050 ALMs	43K LE	232	2.8 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX65	25,300 ALMs	60K LE	312	4.3 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX95	37,470 ALMs	89K LE	448	5.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX125	49,640 ALMs	118K LE	576	6.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX190	76,120 ALMs	181K LE	656	7.4 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ225	89,600 ALMs	224K LE	800	10.8 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGX260	102,600 ALMs	244K LE	736	8.3 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ300	119,200 ALMs	298K LE	920	14.3 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGZ350	139,400 ALMs	349K LE	1,040	16 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—

Source: Altera Arria II FPGA Family Overview Product Table, Product Catalog 2015. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.