EP2AGX190

AlteraArria II

The EP2AGX190 is an Arria II FPGA from Altera, built on a 40 nm process. It provides 76,120 adaptive logic modules (ALMs) (181,000 logic elements (LEs)), 152,240 flip-flops, 7.4 Mb of block RAM and 656 18×18 multipliers. It offers up to 612 user I/O pins and 16 XCVR transceivers at up to 6.375 Gb/s, with hard PCI Express Gen1 blocks. It is available in 2 packages, from the F780 (29 × 29 mm) to the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.

76,120ALMs

65618×18 multipliers

7.4 MbBlock RAM

612Max. user I/O

16Transceivers (6.375 Gb/s)

Specifications

Vendor	Altera
Family	Arria II
Series	Arria
Process	40 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	76,120
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈152,240
Logic elements (LEs)	181,000
Flip-flops	152,240
Distributed RAM	2,379 Kb
Block RAM	7.4 Mb (840 × 9 Kb)
DSP (18×18 multiplier)	656
Clock management tiles	6

Max. user I/O	612
XCVR transceivers	16 × 6.375 Gb/s
PCI Express	Gen1
Analog / monitor	None
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F780	29 × 29	1.0	372	12
F1152	35 × 35	1.0	612	16

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the EP2AGX190

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC6VLX130TAMD Virtex-6	80,000 LUT6	128K LC	480	9.3 Mb	600	20 GTX 6.6 Gb/s	Gen2	—
5AGXA5Altera Arria V	71,698 ALMs	190K LE	600	11.5 Mb	544	24 XCVR 6.5536 Gb/s	Gen2	—
XC6VLX195TAMD Virtex-6	124,800 LUT6	200K LC	640	12.1 Mb	600	20 GTX 6.6 Gb/s	Gen2	—
RT4G150Microchip RTG4	151,824 LUT4	152K LE	462	5 Mb	720	24 SerDes 3.125 Gb/s	Gen1	—
5AGZE1Altera Arria V	83,020 ALMs	220K LE	800	11.4 Mb	414	24 XCVR 12.5 Gb/s	Gen3	—
MPF200TMicrochip PolarFire	192,000 LUT4	192K LE	588	12 Mb	368	16 SERDES 12.7 Gb/s	Gen2	—

Compare side by side: EP2AGX190 vs XC6VLX130T, EP2AGX190 vs 5AGXA5, EP2AGX190 vs XC6VLX195T, EP2AGX190 vs RT4G150.

Compare the EP2AGX190 with up to three other FPGAs.

EP2AGX190 quick facts

How many LUTs does the EP2AGX190 have?

The EP2AGX190 has 76,120 adaptive logic modules (ALMs) (181,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the EP2AGX190 have?

The EP2AGX190 has 656 18×18 multipliers and 7.4 Mb of block RAM.

Does the EP2AGX190 have transceivers?

Yes, 16 XCVR transceivers at up to 6.375 Gb/s.

What are the alternatives to the EP2AGX190?

Devices of similar size in other families include XC6VLX130T (AMD Virtex-6), 5AGXA5 (Altera Arria V), XC6VLX195T (AMD Virtex-6).

Which software is used to design with the EP2AGX190?

Designs for the EP2AGX190 are built with Altera Quartus Prime.

Other Arria II devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
EP2AGX45	18,050 ALMs	43K LE	232	2.8 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX65	25,300 ALMs	60K LE	312	4.3 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX95	37,470 ALMs	89K LE	448	5.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX125	49,640 ALMs	118K LE	576	6.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX190	76,120 ALMs	181K LE	656	7.4 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ225	89,600 ALMs	224K LE	800	10.8 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGX260	102,600 ALMs	244K LE	736	8.3 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ300	119,200 ALMs	298K LE	920	14.3 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGZ350	139,400 ALMs	349K LE	1,040	16 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—

Source: Altera Arria II FPGA Family Overview Product Table, Product Catalog 2015. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.