EP2AGX65

AlteraArria II

The EP2AGX65 is an Arria II FPGA from Altera, built on a 40 nm process. It provides 25,300 adaptive logic modules (ALMs) (60,000 logic elements (LEs)), 50,600 flip-flops, 4.3 Mb of block RAM and 312 18×18 multipliers. It offers up to 364 user I/O pins and 8 XCVR transceivers at up to 6.375 Gb/s, with hard PCI Express Gen1 blocks. It is available in 3 packages, from the U358 (17 × 17 mm) to the F780 (29 × 29 mm). Designs are built with Altera Quartus Prime.

25,300ALMs

31218×18 multipliers

4.3 MbBlock RAM

364Max. user I/O

8Transceivers (6.375 Gb/s)

Specifications

Vendor	Altera
Family	Arria II
Series	Arria
Process	40 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	25,300
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈50,600
Logic elements (LEs)	60,000
Flip-flops	50,600
Distributed RAM	791 Kb
Block RAM	4.3 Mb (495 × 9 Kb)
DSP (18×18 multiplier)	312
Clock management tiles	4

Max. user I/O	364
XCVR transceivers	8 × 6.375 Gb/s
PCI Express	Gen1
Analog / monitor	None
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
U358	17 × 17	0.8	156	4
F572	25 × 25	1.0	252	8
F780	29 × 29	1.0	364	8

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the EP2AGX65

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
XC7K70TAMD Kintex-7	41,000 LUT6	65.6K LC	240	4.7 Mb	300	8 GTX 12.5 Gb/s	Gen2	—
XC6VLX75TAMD Virtex-6	46,560 LUT6	74.5K LC	288	5.5 Mb	360	12 GTX 6.6 Gb/s	Gen2	—
XCAU10PAMD Artix UltraScale+	44,000 LUT6	96K SLC	400	3.5 Mb	228	12 GTH 16.3 Gb/s	Gen4	—
5AGXA1Altera Arria V	28,302 ALMs	75K LE	240	7.8 Mb	416	9 XCVR 6.5536 Gb/s	Gen2	—
XCAU7PAMD Artix UltraScale+	37,000 LUT6	82K SLC	216	3.8 Mb	248	4 GTH 16.3 Gb/s	Gen3	—
EP4CGX75Altera Cyclone IV	74,000 LUT4	74K LE	198	4.1 Mb	310	8 XCVR 3.125 Gb/s	Gen2	—

Compare side by side: EP2AGX65 vs XC7K70T, EP2AGX65 vs XC6VLX75T, EP2AGX65 vs XCAU10P, EP2AGX65 vs 5AGXA1.

Compare the EP2AGX65 with up to three other FPGAs.

EP2AGX65 quick facts

How many LUTs does the EP2AGX65 have?

The EP2AGX65 has 25,300 adaptive logic modules (ALMs) (60,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the EP2AGX65 have?

The EP2AGX65 has 312 18×18 multipliers and 4.3 Mb of block RAM.

Does the EP2AGX65 have transceivers?

Yes, 8 XCVR transceivers at up to 6.375 Gb/s.

What are the alternatives to the EP2AGX65?

Devices of similar size in other families include XC7K70T (AMD Kintex-7), XC6VLX75T (AMD Virtex-6), XCAU10P (AMD Artix UltraScale+).

Which software is used to design with the EP2AGX65?

Designs for the EP2AGX65 are built with Altera Quartus Prime.

Other Arria II devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
EP2AGX45	18,050 ALMs	43K LE	232	2.8 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX65	25,300 ALMs	60K LE	312	4.3 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX95	37,470 ALMs	89K LE	448	5.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX125	49,640 ALMs	118K LE	576	6.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX190	76,120 ALMs	181K LE	656	7.4 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ225	89,600 ALMs	224K LE	800	10.8 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGX260	102,600 ALMs	244K LE	736	8.3 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ300	119,200 ALMs	298K LE	920	14.3 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGZ350	139,400 ALMs	349K LE	1,040	16 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—

Source: Altera Arria II FPGA Family Overview Product Table, Product Catalog 2015. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.