EP2AGZ350

AlteraArria II

The EP2AGZ350 is an Arria II FPGA from Altera, built on a 40 nm process. It provides 139,400 adaptive logic modules (ALMs) (349,000 logic elements (LEs)), 278,800 flip-flops, 16 Mb of block RAM and 1,040 18×18 multipliers. It offers up to 734 user I/O pins and 24 XCVR transceivers at up to 6.375 Gb/s, with hard PCI Express Gen2 blocks. It is available in 3 packages, from the H780 (33 × 33 mm) to the F1517 (40 × 40 mm). Designs are built with Altera Quartus Prime.

139,400ALMs

1,04018×18 multipliers

16 MbBlock RAM

734Max. user I/O

24Transceivers (6.375 Gb/s)

Specifications

Vendor	Altera
Family	Arria II
Series	Arria
Process	40 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	139,400
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈278,800
Logic elements (LEs)	349,000
Flip-flops	278,800
Distributed RAM	4,420 Kb
Block RAM	16 Mb (1248 × 9 Kb)
DSP (18×18 multiplier)	1,040
Clock management tiles	8

Max. user I/O	734
XCVR transceivers	24 × 6.375 Gb/s
PCI Express	Gen2
Analog / monitor	None
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
H780	33 × 33	1.0	281	16
F1152	35 × 35	1.0	554	16
F1517	40 × 40	1.0	734	24

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the EP2AGZ350

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
5AGXB3Altera Arria V	136,880 ALMs	362K LE	1,045	16.9 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5AGTD3Altera Arria V	136,880 ALMs	362K LE	1,045	16.9 Mb	704	18 XCVR/XCVR 10.3125 Gb/s	Gen2	—
5AGXB1Altera Arria V	113,208 ALMs	300K LE	920	14.8 Mb	704	24 XCVR 6.5536 Gb/s	Gen2	—
5SGSD4Altera Stratix V	135,840 ALMs	360K LE	1,044	18.7 Mb	696	36 GX 14.1 Gb/s	Gen3	—
5AGXB5Altera Arria V	158,491 ALMs	420K LE	1,092	20.1 Mb	704	36 XCVR 6.5536 Gb/s	Gen2	—
XC6VLX240TAMD Virtex-6	150,720 LUT6	241K LC	768	14.6 Mb	720	24 GTX 6.6 Gb/s	Gen2	—

Compare side by side: EP2AGZ350 vs 5AGXB3, EP2AGZ350 vs 5AGTD3, EP2AGZ350 vs 5AGXB1.

Compare the EP2AGZ350 with up to three other FPGAs.

EP2AGZ350 quick facts

How many LUTs does the EP2AGZ350 have?

The EP2AGZ350 has 139,400 adaptive logic modules (ALMs) (349,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the EP2AGZ350 have?

The EP2AGZ350 has 1,040 18×18 multipliers and 16 Mb of block RAM.

Does the EP2AGZ350 have transceivers?

Yes, 24 XCVR transceivers at up to 6.375 Gb/s.

What are the alternatives to the EP2AGZ350?

Devices of similar size in other families include 5AGXB3 (Altera Arria V), 5AGTD3 (Altera Arria V), 5AGXB1 (Altera Arria V).

Which software is used to design with the EP2AGZ350?

Designs for the EP2AGZ350 are built with Altera Quartus Prime.

Other Arria II devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
EP2AGX45	18,050 ALMs	43K LE	232	2.8 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX65	25,300 ALMs	60K LE	312	4.3 Mb	364	8 XCVR 6.375 Gb/s	Gen1	—
EP2AGX95	37,470 ALMs	89K LE	448	5.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX125	49,640 ALMs	118K LE	576	6.4 Mb	452	12 XCVR 6.375 Gb/s	Gen1	—
EP2AGX190	76,120 ALMs	181K LE	656	7.4 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ225	89,600 ALMs	224K LE	800	10.8 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGX260	102,600 ALMs	244K LE	736	8.3 Mb	612	16 XCVR 6.375 Gb/s	Gen1	—
EP2AGZ300	119,200 ALMs	298K LE	920	14.3 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—
EP2AGZ350	139,400 ALMs	349K LE	1,040	16 Mb	734	24 XCVR 6.375 Gb/s	Gen2	—

Source: Altera Arria II FPGA Family Overview Product Table, Product Catalog 2015. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.