DX 1100

AlteraStratix 10 DX

The DX 1100 is a Stratix 10 DX FPGA from Altera, built on a 14 nm process. It provides 449,280 adaptive logic modules (ALMs) (1,325,000 logic elements (LEs)), 1,797,120 flip-flops, 107 Mb of block RAM and 2,592 variable-precision DSP blocks. Versions with the optional hard processor system include four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 528 user I/O pins and 32 GXP/GXE transceivers at up to 57.8 Gb/s, with hard PCI Express Gen4 x16 blocks. It comes in a single package, the F1760 (42.5 × 42.5 mm). Designs are built with Altera Quartus Prime.

449,280ALMs

2,592variable-precision DSP blocks

107 MbBlock RAM

528Max. user I/O

32Transceivers (57.8 Gb/s)

4× A53Hard processor

Specifications

Vendor	Altera
Family	Stratix 10 DX
Series	Stratix
Process	14 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	449,280
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈898,560
Logic elements (LEs)	1,325,000
Flip-flops	1,797,120
Distributed RAM	7,168 Kb
Block RAM	107 Mb (5461 × 20 Kb)
DSP (variable-precision DSP block)	2,592

Max. user I/O	528
Differential pairs	264
GXP transceivers	16 × 16 Gb/s
GXE transceivers	16 × 57.8 Gb/s
PCI Express (PL)	Gen4 x16
100G Ethernet MAC	4
Analog / monitor	None
Hard processor	4× Arm Cortex-A53 @ 1.5 GHz (optional, HPS variants)
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F1760	42.5 × 42.5	1.0	528	32

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the DX 1100

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
SX 1100Altera Stratix 10 GX/SX	449,280 ALMs	1325K LE	2,592	107 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3	—
XC2VP3102AMD Versal Premium Gen 2	643,456 LUT6	1408K SLC	3,332	44 Mb	438	32 GTM2 112 Gb/s	Gen6	—
A5D 110Altera Agilex 5 D-Series	364,000 ALMs	1074K LE	3,312	104.3 Mb	616	24 XCVR 28 Gb/s	Gen4	—
XCVR1602AMD Versal RF	551,040 LUT6	1205K SLC	2,256	39 Mb	470	20 GTYP/GTM 58 Gb/s	Gen5	—
XCVR1652AMD Versal RF	551,040 LUT6	1205K SLC	2,256	39 Mb	470	20 GTYP/GTM 58 Gb/s	Gen5	—
AGF 012Altera Agilex 7 F-Series	399,500 ALMs	1179K LE	3,743	115 Mb	768	32 XCVR 58 Gb/s	—	—

Compare side by side: DX 1100 vs SX 1100, DX 1100 vs XC2VP3102, DX 1100 vs A5D 110, DX 1100 vs XCVR1602, DX 1100 vs XCVR1652.

Compare the DX 1100 with up to three other FPGAs.

DX 1100 quick facts

How many LUTs does the DX 1100 have?

The DX 1100 has 449,280 adaptive logic modules (ALMs) (1,325,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the DX 1100 have?

The DX 1100 has 2,592 variable-precision DSP blocks and 107 Mb of block RAM.

Does the DX 1100 have transceivers?

Yes, 32 GXP/GXE transceivers at up to 57.8 Gb/s.

Does the DX 1100 have a processor?

Yes. Variants with the optional hard processor system include a 4× Arm Cortex-A53 processor.

What are the alternatives to the DX 1100?

Devices of similar size in other families include SX 1100 (Altera Stratix 10 GX/SX), XC2VP3102 (AMD Versal Premium Gen 2), A5D 110 (Altera Agilex 5 D-Series).

Which software is used to design with the DX 1100?

Designs for the DX 1100 are built with Altera Quartus Prime.

Other Stratix 10 DX devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
DX 1100	449,280 ALMs	1325K LE	2,592	107 Mb	528	32 GXP/GXE 57.8 Gb/s	Gen4	—
DX 2100	702,720 ALMs	2073K LE	3,960	134 Mb	612	84 GXP/GXE 57.8 Gb/s	Gen4	—
DX 2800	933,120 ALMs	2753K LE	5,760	229 Mb	816	84 GXP/GXE 57.8 Gb/s	Gen4	—

Source: Altera Stratix 10 DX FPGA Product Table, 2025.09.23. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.