TX 400

AlteraStratix 10 TX

The TX 400 is a Stratix 10 TX FPGA from Altera, built on a 14 nm process. It provides 128,160 adaptive logic modules (ALMs) (378,000 logic elements (LEs)), 512,640 flip-flops, 30 Mb of block RAM and 648 variable-precision DSP blocks. Versions with the optional hard processor system include four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 384 user I/O pins and 24 GXE transceivers at up to 57.8 Gb/s. It comes in a single package, the F1152 (35 × 35 mm). Designs are built with Altera Quartus Prime.

128,160ALMs

648variable-precision DSP blocks

30 MbBlock RAM

384Max. user I/O

24Transceivers (57.8 Gb/s)

4× A53Hard processor

Specifications

Vendor	Altera
Family	Stratix 10 TX
Series	Stratix
Process	14 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	128,160
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈256,320
Logic elements (LEs)	378,000
Flip-flops	512,640
Distributed RAM	2,048 Kb
Block RAM	30 Mb (1537 × 20 Kb)
DSP (variable-precision DSP block)	648

Max. user I/O	384
Differential pairs	144
GXE transceivers	24 × 57.8 Gb/s
PCI Express (PL)	None
100G Ethernet MAC	4
Analog / monitor	None
Hard processor	4× Arm Cortex-A53 @ 1.5 GHz (optional, HPS variants)
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F1152	35 × 35	1.0	384	24

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the TX 400

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
SX 400Altera Stratix 10 GX/SX	128,160 ALMs	378K LE	648	30 Mb	374	24 XCVR/XCVR 28.3 Gb/s	Gen3	—
A5E 052AAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 28 Gb/s	Gen4	—
A5E 052BAltera Agilex 5 E-Series	177,600 ALMs	524K LE	676	25.2 Mb	504	24 XCVR 17 Gb/s	Gen4	—
A5E 043AAltera Agilex 5 E-Series	147,200 ALMs	434K LE	564	20.5 Mb	504	16 XCVR 28 Gb/s	Gen4	—
A5E 043BAltera Agilex 5 E-Series	147,200 ALMs	434K LE	564	20.5 Mb	504	16 XCVR 17 Gb/s	Gen4	—
Ti260Efinix Titanium	— 264K LEs, LUTs not published	264K LE	960	19.7 Mb	310	16 SERDES 16 Gb/s	Gen4	—

Compare side by side: TX 400 vs SX 400, TX 400 vs A5E 052A, TX 400 vs A5E 052B.

Compare the TX 400 with up to three other FPGAs.

TX 400 quick facts

How many LUTs does the TX 400 have?

The TX 400 has 128,160 adaptive logic modules (ALMs) (378,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the TX 400 have?

The TX 400 has 648 variable-precision DSP blocks and 30 Mb of block RAM.

Does the TX 400 have transceivers?

Yes, 24 GXE transceivers at up to 57.8 Gb/s.

Does the TX 400 have a processor?

Yes. Variants with the optional hard processor system include a 4× Arm Cortex-A53 processor.

What are the alternatives to the TX 400?

Devices of similar size in other families include SX 400 (Altera Stratix 10 GX/SX), A5E 052A (Altera Agilex 5 E-Series), A5E 052B (Altera Agilex 5 E-Series).

Which software is used to design with the TX 400?

Designs for the TX 400 are built with Altera Quartus Prime.

Other Stratix 10 TX devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
TX 400	128,160 ALMs	378K LE	648	30 Mb	384	24 GXE 57.8 Gb/s	—	—
TX 850	284,960 ALMs	841K LE	2,016	68 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1100	449,280 ALMs	1325K LE	2,592	107 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1650	569,200 ALMs	1679K LE	3,326	120 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2100	702,720 ALMs	2073K LE	3,960	134 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2500	821,150 ALMs	2422K LE	5,011	195 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2800	933,120 ALMs	2753K LE	5,760	229 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—

Source: Altera Stratix 10 TX FPGA Product Table, 2024.02.29. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.