TX 850

AlteraStratix 10 TX

The TX 850 is a Stratix 10 TX FPGA from Altera, built on a 14 nm process. It provides 284,960 adaptive logic modules (ALMs) (841,000 logic elements (LEs)), 1,139,840 flip-flops, 68 Mb of block RAM and 2,016 variable-precision DSP blocks. Versions with the optional hard processor system include four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 440 user I/O pins and 72 GXE/GXT/GX transceivers at up to 57.8 Gb/s, with hard PCI Express Gen3 x16 blocks. It is available in 2 packages, from the F1760 (42.5 × 42.5 mm) to the F2397 (50 × 50 mm). Designs are built with Altera Quartus Prime.

284,960ALMs

2,016variable-precision DSP blocks

68 MbBlock RAM

440Max. user I/O

72Transceivers (57.8 Gb/s)

4× A53Hard processor

Specifications

Vendor	Altera
Family	Stratix 10 TX
Series	Stratix
Process	14 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	284,960
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈569,920
Logic elements (LEs)	841,000
Flip-flops	1,139,840
Distributed RAM	4,096 Kb
Block RAM	68 Mb (3477 × 20 Kb)
DSP (variable-precision DSP block)	2,016

Max. user I/O	440
Differential pairs	216
GXE transceivers	48 × 57.8 Gb/s
GXT transceivers	16 × 28.3 Gb/s
GX transceivers	8 × 17.4 Gb/s
PCI Express (PL)	Gen3 x16
100G Ethernet MAC	9
Analog / monitor	None
Hard processor	4× Arm Cortex-A53 @ 1.5 GHz (optional, HPS variants)
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F1760	42.5 × 42.5	1.0	440	48
F2397	50 × 50	1.0	440	72

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the TX 850

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
SX 850Altera Stratix 10 GX/SX	284,960 ALMs	841K LE	2,016	68 Mb	688	48 XCVR/XCVR 28.3 Gb/s	Gen3	—
XCZU17EGAMD Zynq UltraScale+ MPSoC	423,000 LUT6	926K SLC	1,590	28 Mb	668	72 GTH/GTY 32.75 Gb/s	Gen3	—
XCZU19EGAMD Zynq UltraScale+ MPSoC	523,000 LUT6	1143K SLC	1,968	34.6 Mb	668	72 GTH/GTY 32.75 Gb/s	Gen3	—
AGF 008Altera Agilex 7 F-Series	259,200 ALMs	765K LE	2,296	74 Mb	576	32 XCVR 58 Gb/s	—	—
A5D 064Altera Agilex 5 D-Series	218,400 ALMs	644K LE	1,840	62.6 Mb	444	32 XCVR 28 Gb/s	Gen4	—
XCZU11EGAMD Zynq UltraScale+ MPSoC	299,000 LUT6	653K SLC	2,928	21.1 Mb	512	48 GTH/GTY 32.75 Gb/s	Gen3	—

Compare side by side: TX 850 vs SX 850, TX 850 vs XCZU17EG, TX 850 vs XCZU19EG, TX 850 vs AGF 008.

Compare the TX 850 with up to three other FPGAs.

TX 850 quick facts

How many LUTs does the TX 850 have?

The TX 850 has 284,960 adaptive logic modules (ALMs) (841,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the TX 850 have?

The TX 850 has 2,016 variable-precision DSP blocks and 68 Mb of block RAM.

Does the TX 850 have transceivers?

Yes, 72 GXE/GXT/GX transceivers at up to 57.8 Gb/s.

Does the TX 850 have a processor?

Yes. Variants with the optional hard processor system include a 4× Arm Cortex-A53 processor.

What are the alternatives to the TX 850?

Devices of similar size in other families include SX 850 (Altera Stratix 10 GX/SX), XCZU17EG (AMD Zynq UltraScale+ MPSoC), XCZU19EG (AMD Zynq UltraScale+ MPSoC).

Which software is used to design with the TX 850?

Designs for the TX 850 are built with Altera Quartus Prime.

Other Stratix 10 TX devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
TX 400	128,160 ALMs	378K LE	648	30 Mb	384	24 GXE 57.8 Gb/s	—	—
TX 850	284,960 ALMs	841K LE	2,016	68 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1100	449,280 ALMs	1325K LE	2,592	107 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1650	569,200 ALMs	1679K LE	3,326	120 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2100	702,720 ALMs	2073K LE	3,960	134 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2500	821,150 ALMs	2422K LE	5,011	195 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2800	933,120 ALMs	2753K LE	5,760	229 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—

Source: Altera Stratix 10 TX FPGA Product Table, 2024.02.29. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.