TX 2500

AlteraStratix 10 TX

The TX 2500 is a Stratix 10 TX FPGA from Altera, built on a 14 nm process. It provides 821,150 adaptive logic modules (ALMs) (2,422,000 logic elements (LEs)), 3,284,600 flip-flops, 195 Mb of block RAM and 5,011 variable-precision DSP blocks. Versions with the optional hard processor system include four Arm Cortex-A53 cores running at up to 1.5 GHz. The programmable logic offers up to 440 user I/O pins and 144 GXE/GXT/GX transceivers at up to 57.8 Gb/s, with hard PCI Express Gen3 x16 blocks. It is available in 2 packages, from the F2397 (50 × 50 mm) to the F2912 (55 × 55 mm). Designs are built with Altera Quartus Prime.

821,150ALMs

5,011variable-precision DSP blocks

195 MbBlock RAM

440Max. user I/O

144Transceivers (57.8 Gb/s)

4× A53Hard processor

Specifications

Vendor	Altera
Family	Stratix 10 TX
Series	Stratix
Process	14 nm
Configuration memory	SRAM
Adaptive logic modules (ALMs)	821,150
Logic block	adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions)
LUT note	Adaptive logic modules (ALMs): fracturable 8-input LUTs; each ALM can implement two 4-input functions
LUT4 equivalent (approx.)	≈1,642,300
Logic elements (LEs)	2,422,000
Flip-flops	3,284,600
Distributed RAM	13,312 Kb
Block RAM	195 Mb (9963 × 20 Kb)
DSP (variable-precision DSP block)	5,011

Max. user I/O	440
Differential pairs	216
GXE transceivers	120 × 57.8 Gb/s
GXT transceivers	16 × 28.3 Gb/s
GX transceivers	8 × 17.4 Gb/s
PCI Express (PL)	Gen3 x16
100G Ethernet MAC	21
Analog / monitor	None
Hard processor	4× Arm Cortex-A53 @ 1.5 GHz (optional, HPS variants)
Design tool	Altera Quartus Prime

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
F2397	50 × 50	1.0	440	96
F2912	55 × 55	1.0	296	144

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Alternatives to the TX 2500

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
AGI 022Altera Agilex 7 I-Series	748,500 ALMs	2208K LE	6,250	212 Mb	720	64 XCVR 116 Gb/s	—	—
AGF 022Altera Agilex 7 F-Series	748,500 ALMs	2208K LE	6,250	212 Mb	744	64 XCVR 58 Gb/s	—	—
SX 2500Altera Stratix 10 GX/SX	821,150 ALMs	2422K LE	5,011	195 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3	—
SX 2100Altera Stratix 10 GX/SX	679,680 ALMs	2005K LE	3,744	127 Mb	704	96 XCVR/XCVR 28.3 Gb/s	Gen3	—
SX 2800Altera Stratix 10 GX/SX	933,120 ALMs	2753K LE	5,760	229 Mb	1,160	96 XCVR/XCVR 28.3 Gb/s	Gen3	—
XC2VP3402AMD Versal Premium Gen 2	1,170,816 LUT6	2561K SLC	6,080	78 Mb	736	56 GTM2 112 Gb/s	Gen6	—

Compare side by side: TX 2500 vs AGI 022, TX 2500 vs AGF 022, TX 2500 vs SX 2500, TX 2500 vs SX 2100.

Compare the TX 2500 with up to three other FPGAs.

TX 2500 quick facts

How many LUTs does the TX 2500 have?

The TX 2500 has 821,150 adaptive logic modules (ALMs) (2,422,000 logic elements (les) as published by Altera). Logic block: adaptive logic module: fracturable 8-input LUT (one 6-input or two independent 4-input functions).

How many DSP blocks does the TX 2500 have?

The TX 2500 has 5,011 variable-precision DSP blocks and 195 Mb of block RAM.

Does the TX 2500 have transceivers?

Yes, 144 GXE/GXT/GX transceivers at up to 57.8 Gb/s.

Does the TX 2500 have a processor?

Yes. Variants with the optional hard processor system include a 4× Arm Cortex-A53 processor.

What are the alternatives to the TX 2500?

Devices of similar size in other families include AGI 022 (Altera Agilex 7 I-Series), AGF 022 (Altera Agilex 7 F-Series), SX 2500 (Altera Stratix 10 GX/SX).

Which software is used to design with the TX 2500?

Designs for the TX 2500 are built with Altera Quartus Prime.

Other Stratix 10 TX devices

Device	LUTs	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe	CoreScore
TX 400	128,160 ALMs	378K LE	648	30 Mb	384	24 GXE 57.8 Gb/s	—	—
TX 850	284,960 ALMs	841K LE	2,016	68 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1100	449,280 ALMs	1325K LE	2,592	107 Mb	440	72 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 1650	569,200 ALMs	1679K LE	3,326	120 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2100	702,720 ALMs	2073K LE	3,960	134 Mb	440	96 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2500	821,150 ALMs	2422K LE	5,011	195 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—
TX 2800	933,120 ALMs	2753K LE	5,760	229 Mb	440	144 GXE/GXT/GX 57.8 Gb/s	Gen3	—

Source: Altera Stratix 10 TX FPGA Product Table, 2024.02.29. Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.