XCSU10P
AMDSpartan UltraScale+The XCSU10P is a Spartan UltraScale+ FPGA from AMD, built on a 16 nm process. It provides 5,000 LUT6 look-up tables (11,000 system logic cells), about 8,000 LUT4 equivalents, 10,000 flip-flops, 1.7 Mb of block RAM and 24 DSP slices. It offers up to 304 user I/O pins. It is available in 3 packages, from the CMVA361 (10 × 10 mm) to the SBVB625 (21 × 21 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Spartan UltraScale+ |
| Series | UltraScale+ |
| Process | 16 nm |
| Configuration memory | SRAM |
| LUT4-equivalent capacity | 8,000 |
| Look-up tables (LUT6) | 5,000 |
| System logic cells | 11,000 |
| Flip-flops | 10,000 |
| Distributed RAM | 72 Kb |
| Block RAM | 1.7 Mb (48 × 36 Kb) |
| DSP (DSP slice) | 24 |
| Clock management tiles | 2 |
| Max. user I/O | 304 |
|---|---|
| HD I/O | 252 |
| HP I/O | 52 |
| Transceivers | None |
| PCI Express | None |
| Analog / monitor | System Monitor |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | Transceivers |
|---|---|---|---|---|
| CMVA361 | 10 × 10 | 0.5 | 220 | — |
| CMVA529 | 12 × 12 | 0.5 | 304 | — |
| SBVB625 | 21 × 21 | 0.8 | 304 | — |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Extended (E) | 0 to 100 °C | -1, -2 |
| Industrial (I) | −40 to 100 °C | -1, -2, -1L |
Alternatives to the XCSU10P
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| GW1N-9Gowin LittleBee | 8.6K 8.6K LUT4 | — | 20 | 0.5 Mb | 276 | — | — |
| GW1NR-9Gowin LittleBee | 8.6K 8.6K LUT4 | — | 20 | 0.5 Mb | 276 | — | — |
| LFMXO5-15DLattice MachXO5-NX | 11.7K 11.7K LUT4 | 14K LC | 16 | 0.3 Mb | 305 | — | — |
| 10M08Altera MAX 10 | 8K 8K LUT4 | 8K LE | 24 | 0.4 Mb | 250 | — | — |
| T13Efinix Trion | ≈12.8K 12.8K LEs | 12.8K LE | 24 | 0.7 Mb | 195 | — | — |
| LFE5U-12Lattice ECP5 | 12K 12K LUT4 | — | 28 | 0.6 Mb | 197 | — | — |
Compare side by side: XCSU10P vs GW1N-9, XCSU10P vs GW1NR-9, XCSU10P vs LFMXO5-15D.
XCSU10P quick facts
How many LUTs does the XCSU10P have?
The XCSU10P has 5,000 LUT6 look-up tables, about 8,000 LUT4 equivalents (11,000 system logic cells as published by AMD).
How many DSP blocks does the XCSU10P have?
The XCSU10P has 24 DSP slices and 1.7 Mb of block RAM.
Does the XCSU10P have transceivers?
No, the XCSU10P has no multi-gigabit transceivers. Its user I/O supports up to 304 pins.
What are the alternatives to the XCSU10P?
Devices of similar size in other families include GW1N-9 (Gowin LittleBee), GW1NR-9 (Gowin LittleBee), LFMXO5-15D (Lattice MachXO5-NX).
Which software is used to design with the XCSU10P?
Designs for the XCSU10P are built with AMD Vivado.
Other Spartan UltraScale+ devices
| Device | LUT4-eq. | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe |
|---|---|---|---|---|---|---|---|
| XCSU10P | 8K 5K LUT6 | 11K SLC | 24 | 1.7 Mb | 304 | — | — |
| XCSU25P | 16K 10K LUT6 | 22K SLC | 36 | 1.7 Mb | 304 | — | — |
| XCSU35P | 25.6K 16K LUT6 | 36K SLC | 48 | 1.7 Mb | 304 | — | — |
| XCSU45P | 38.4K 24K LUT6 | 53K SLC | 96 | 2.5 Mb | 262 | 4 GTH 16.3 Gb/s | Gen4 |
| XCSU60P | 48K 30K LUT6 | 66K SLC | 144 | 3.4 Mb | 262 | 4 GTH 16.3 Gb/s | Gen4 |
| XCSU65P | 48K 30K LUT6 | 66K SLC | 144 | 3.8 Mb | 478 | 4 GTH 16.3 Gb/s | Gen4 |
| XCSU100P | 73.6K 46K LUT6 | 101K SLC | 144 | 5.1 Mb | 478 | 4 GTH 16.3 Gb/s | Gen4 |
| XCSU150P | 101K 63K LUT6 | 138K SLC | 384 | 5.9 Mb | 572 | 8 GTH 16.3 Gb/s | Gen4 |
| XCSU200P | 160K 100K LUT6 | 219K SLC | 384 | 6.8 Mb | 572 | 8 GTH 16.3 Gb/s | Gen4 |
Source: AMD UltraScale+ FPGAs Product Selection Guide, XMP103 (v2.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.