XCSU25P

AMDSpartan UltraScale+

The XCSU25P is a Spartan UltraScale+ FPGA from AMD, built on a 16 nm process. It provides 10,000 LUT6 look-up tables (22,000 system logic cells), about 16,000 LUT4 equivalents, 20,000 flip-flops, 1.7 Mb of block RAM and 36 DSP slices. It offers up to 304 user I/O pins. It is available in 3 packages, from the CMVA361 (10 × 10 mm) to the SBVB625 (21 × 21 mm). Temperature grades: extended, industrial. Designs are built with AMD Vivado.

16KLUT4-equivalent

10KLUTs (LUT6)

36DSP slices

1.7 MbBlock RAM

304Max. user I/O

—Transceivers

Specifications

Vendor	AMD
Family	Spartan UltraScale+
Series	UltraScale+
Process	16 nm
Configuration memory	SRAM
LUT4-equivalent capacity	16,000
Look-up tables (LUT6)	10,000
System logic cells	22,000
Flip-flops	20,000
Distributed RAM	143 Kb
Block RAM	1.7 Mb (48 × 36 Kb)
DSP (DSP slice)	36
Clock management tiles	2

Max. user I/O	304
HD I/O	252
HP I/O	52
Transceivers	None
PCI Express	None
Analog / monitor	System Monitor
Design tool	AMD Vivado

Packages

Package	Size (mm)	Pitch (mm)	User I/O	Transceivers
CMVA361	10 × 10	0.5	220	—
CMVA529	12 × 12	0.5	304	—
SBVB625	21 × 21	0.8	304	—

Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).

Speed and temperature grades

Temperature grade	Junction range	Speed grades
Extended (E)	0 to 100 °C	-1, -2
Industrial (I)	−40 to 100 °C	-1, -2, -1L

Alternatives to the XCSU25P

Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
T20Efinix Trion	≈19.7K 19.7K LEs	19.7K LE	36	1 Mb	230	—	—
5CEA2Altera Cyclone V	18.9K 9.4K ALMs	25K LE	25	1.7 Mb	224	—	—
LFMXO5-20TDLattice MachXO5-NX	16.7K 16.7K LUT4	20K LC	48	0.7 Mb	368	1 SERDES	Gen2
GW3A-20Gowin Arora III	23K 23K LUT4	—	52	2.1 Mb	238	—	—
GW5A-25Gowin Arora V	23K 23K LUT4	—	28	1 Mb	239	—	—
GW5AR-25Gowin Arora V	23K 23K LUT4	—	28	1 Mb	239	—	—

Compare side by side: XCSU25P vs T20, XCSU25P vs 5CEA2, XCSU25P vs LFMXO5-20TD.

XCSU25P quick facts

How many LUTs does the XCSU25P have?

The XCSU25P has 10,000 LUT6 look-up tables, about 16,000 LUT4 equivalents (22,000 system logic cells as published by AMD).

How many DSP blocks does the XCSU25P have?

The XCSU25P has 36 DSP slices and 1.7 Mb of block RAM.

Does the XCSU25P have transceivers?

No, the XCSU25P has no multi-gigabit transceivers. Its user I/O supports up to 304 pins.

What are the alternatives to the XCSU25P?

Devices of similar size in other families include T20 (Efinix Trion), 5CEA2 (Altera Cyclone V), LFMXO5-20TD (Lattice MachXO5-NX).

Which software is used to design with the XCSU25P?

Designs for the XCSU25P are built with AMD Vivado.

Other Spartan UltraScale+ devices

Device	LUT4-eq.	Vendor logic	DSP	Block RAM	Max I/O	Transceivers	PCIe
XCSU10P	8K 5K LUT6	11K SLC	24	1.7 Mb	304	—	—
XCSU25P	16K 10K LUT6	22K SLC	36	1.7 Mb	304	—	—
XCSU35P	25.6K 16K LUT6	36K SLC	48	1.7 Mb	304	—	—
XCSU45P	38.4K 24K LUT6	53K SLC	96	2.5 Mb	262	4 GTH 16.3 Gb/s	Gen4
XCSU60P	48K 30K LUT6	66K SLC	144	3.4 Mb	262	4 GTH 16.3 Gb/s	Gen4
XCSU65P	48K 30K LUT6	66K SLC	144	3.8 Mb	478	4 GTH 16.3 Gb/s	Gen4
XCSU100P	73.6K 46K LUT6	101K SLC	144	5.1 Mb	478	4 GTH 16.3 Gb/s	Gen4
XCSU150P	101K 63K LUT6	138K SLC	384	5.9 Mb	572	8 GTH 16.3 Gb/s	Gen4
XCSU200P	160K 100K LUT6	219K SLC	384	6.8 Mb	572	8 GTH 16.3 Gb/s	Gen4

Source: AMD UltraScale+ FPGAs Product Selection Guide, XMP103 (v2.8). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.