XCZU21DR
AMDZynq UltraScale+ RFSoCSoCThe XCZU21DR is a Zynq UltraScale+ RFSoC FPGA from AMD, built on a 16 nm process. It provides 425,000 LUT6 look-up tables (930,000 system logic cells), 850,000 flip-flops, 38 Mb of block RAM plus 22.5 Mb of UltraRAM and 4,272 DSP slices. Its processing system includes four Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 280 user I/O pins and 16 GTY transceivers at up to 28.21 Gb/s, with hard PCI Express Gen3 x16 blocks. It comes in a single package, the D1156 (35 × 35 mm). Temperature grades: industrial, extended. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Zynq UltraScale+ RFSoC |
| Series | UltraScale+ |
| Process | 16 nm |
| Configuration memory | SRAM |
| Look-up tables (LUT6) | 425,000 |
| Logic block | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈680,000 |
| System logic cells | 930,000 |
| Flip-flops | 850,000 |
| Distributed RAM | 13,312 Kb |
| Block RAM | 38 Mb |
| UltraRAM | 22.5 Mb |
| DSP (DSP slice) | 4,272 |
| Max. user I/O | 280 |
|---|---|
| GTY transceivers | 16 × 28.21 Gb/s |
| PCI Express (PL) | 2× Gen3 x16 |
| 100G Ethernet MAC | 2 |
| Analog / monitor | System Monitor |
| Hard processor | 4× Arm Cortex-A53 @ 1.3 GHz |
| Real-time processor | Dual Arm Cortex-R5F |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | PS I/O | Transceivers |
|---|---|---|---|---|---|
| D1156 | 35 × 35 | 1.0 | 280 | 214 | 16 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Industrial (I) | −40 to 100 °C | -1, -1L, -2, -2L |
| Extended (E) | 0 to 100 °C | -1, -2, -2L |
Alternatives to the XCZU21DR
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCZU15EGAMD Zynq UltraScale+ MPSoC | 341,000 LUT6 | 747K SLC | 3,528 | 26.2 Mb | 328 | 24 GTH 16.3 Gb/s | — | — |
| A5D 110Altera Agilex 5 D-Series | 364,000 ALMs | 1074K LE | 3,312 | 104.3 Mb | 616 | 24 XCVR 28 Gb/s | Gen4 | — |
| AGF 008Altera Agilex 7 F-Series | 259,200 ALMs | 765K LE | 2,296 | 74 Mb | 576 | 32 XCVR 58 Gb/s | — | — |
| XC2VE3804AMD Versal AI Edge Gen 2 | 543,104 LUT6 | 1188K SLC | 2,064 | 47.2 Mb | 556 | 20 GTYP 32.75 Gb/s | Gen5 | — |
| XC2VE3858AMD Versal AI Edge Gen 2 | 543,104 LUT6 | 1188K SLC | 2,064 | 47.2 Mb | 556 | 20 GTYP 32.75 Gb/s | Gen5 | — |
| XC2VM3858AMD Versal Prime Gen 2 | 543,104 LUT6 | 1188K SLC | 2,064 | 47.2 Mb | 556 | 20 GTYP 32.75 Gb/s | Gen5 | — |
Compare side by side: XCZU21DR vs XCZU15EG, XCZU21DR vs A5D 110, XCZU21DR vs AGF 008.
Compare the XCZU21DR with up to three other FPGAs.
XCZU21DR quick facts
How many LUTs does the XCZU21DR have?
The XCZU21DR has 425,000 LUT6 look-up tables (930,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.
How many DSP blocks does the XCZU21DR have?
The XCZU21DR has 4,272 DSP slices and 38 Mb of block RAM plus 22.5 Mb of UltraRAM.
Does the XCZU21DR have transceivers?
Yes, 16 GTY transceivers at up to 28.21 Gb/s.
Does the XCZU21DR have a processor?
Yes. It includes a hard 4× Arm Cortex-A53 processor.
What are the alternatives to the XCZU21DR?
Devices of similar size in other families include XCZU15EG (AMD Zynq UltraScale+ MPSoC), A5D 110 (Altera Agilex 5 D-Series), AGF 008 (Altera Agilex 7 F-Series).
Which software is used to design with the XCZU21DR?
Designs for the XCZU21DR are built with AMD Vivado.
Other Zynq UltraScale+ RFSoC devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCZU64DR | 150,000 LUT6 | 328K SLC | 1,872 | 15.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU63DR | 180,000 LUT6 | 393K SLC | 1,200 | 17.6 Mb | 154 | 4 GTY 28.21 Gb/s | — | — |
| XCZU42DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 152 | 8 GTY 28.21 Gb/s | — | — |
| XCZU65DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU67DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU25DR | 310,000 LUT6 | 678K SLC | 3,145 | 27.8 Mb | 347 | 8 GTY 28.21 Gb/s | Gen3 | — |
| XCZU21DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 280 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU27DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU28DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU29DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU39DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU43DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU46DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 360 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU47DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU48DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU49DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen4 | — |
Source: AMD Zynq UltraScale+ RFSoC Product Selection Guide, XMP105 (v1.12.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.