XCZU65DR
AMDZynq UltraScale+ RFSoCSoCThe XCZU65DR is a Zynq UltraScale+ RFSoC FPGA from AMD, built on a 16 nm process. It provides 224,000 LUT6 look-up tables (489,000 system logic cells), 448,000 flip-flops, 22.8 Mb of block RAM plus 45 Mb of UltraRAM and 1,872 DSP slices. Its processing system includes four Arm Cortex-A53 cores running at up to 1.3 GHz, a dual Arm Cortex-R5F real-time processor. The programmable logic offers up to 154 user I/O pins and 8 GTY transceivers at up to 28.21 Gb/s. It comes in a single package, the E1156 (35 × 35 mm). Temperature grades: industrial. Designs are built with AMD Vivado.
Specifications
| Vendor | AMD |
|---|---|
| Family | Zynq UltraScale+ RFSoC |
| Series | UltraScale+ |
| Process | 16 nm |
| Configuration memory | SRAM |
| Look-up tables (LUT6) | 224,000 |
| Logic block | 6-input look-up table, fracturable into two LUT5 with shared inputs |
| LUT4 equivalent (approx.) | ≈358,400 |
| System logic cells | 489,000 |
| Flip-flops | 448,000 |
| Distributed RAM | 6,963 Kb |
| Block RAM | 22.8 Mb |
| UltraRAM | 45 Mb |
| DSP (DSP slice) | 1,872 |
| Max. user I/O | 154 |
|---|---|
| GTY transceivers | 8 × 28.21 Gb/s |
| PCI Express (PL) | None |
| 100G Ethernet MAC | 1 |
| Analog / monitor | 6× 14-bit RF-ADC (5.9 GSPS), 6× 14-bit RF-DAC (10 GSPS) |
| Hard processor | 4× Arm Cortex-A53 @ 1.3 GHz |
| Real-time processor | Dual Arm Cortex-R5F |
| Design tool | AMD Vivado |
Packages
| Package | Size (mm) | Pitch (mm) | User I/O | PS I/O | Transceivers |
|---|---|---|---|---|---|
| E1156 | 35 × 35 | 1.0 | 154 | 214 | 8 |
Package names are shown as in the selection guide; the full ordering code adds speed grade and temperature (see the data sheet).
Speed and temperature grades
| Temperature grade | Junction range | Speed grades |
|---|---|---|
| Industrial (I) | −40 to 100 °C | -1, -1L, -2, -2L |
Alternatives to the XCZU65DR
Closest matches in other families and vendors by logic, DSP, memory, I/O and transceivers. Check pin compatibility and tools before migrating.
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCVM2152AMD Versal Prime | 346,112 LUT6 | 757K SLC | 1,704 | 27 Mb | 428 | 16 GTYP/GTM 58 Gb/s | Gen5 | — |
| XC2VM3654AMD Versal Prime Gen 2 | 318,080 LUT6 | 696K SLC | 1,428 | 22.2 Mb | 310 | 24 GTYP 32.75 Gb/s | Gen5 | — |
| A5D 051Altera Agilex 5 D-Series | 174,600 ALMs | 515K LE | 1,472 | 50.1 Mb | 444 | 24 XCVR 28 Gb/s | Gen4 | — |
| SX 650Altera Stratix 10 GX/SX | 207,360 ALMs | 612K LE | 1,152 | 49 Mb | 392 | 24 XCVR/XCVR 28.3 Gb/s | Gen3 | — |
| A5D 064Altera Agilex 5 D-Series | 218,400 ALMs | 644K LE | 1,840 | 62.6 Mb | 444 | 32 XCVR 28 Gb/s | Gen4 | — |
| XCZU7CGAMD Zynq UltraScale+ MPSoC | 230,000 LUT6 | 504K SLC | 1,728 | 11 Mb | 464 | 24 GTH 16.3 Gb/s | Gen3 | — |
Compare side by side: XCZU65DR vs XCVM2152, XCZU65DR vs XC2VM3654, XCZU65DR vs A5D 051.
Compare the XCZU65DR with up to three other FPGAs.
XCZU65DR quick facts
How many LUTs does the XCZU65DR have?
The XCZU65DR has 224,000 LUT6 look-up tables (489,000 system logic cells as published by AMD). Logic block: 6-input look-up table, fracturable into two LUT5 with shared inputs.
How many DSP blocks does the XCZU65DR have?
The XCZU65DR has 1,872 DSP slices and 22.8 Mb of block RAM plus 45 Mb of UltraRAM.
Does the XCZU65DR have transceivers?
Yes, 8 GTY transceivers at up to 28.21 Gb/s.
Does the XCZU65DR have a processor?
Yes. It includes a hard 4× Arm Cortex-A53 processor.
What are the alternatives to the XCZU65DR?
Devices of similar size in other families include XCVM2152 (AMD Versal Prime), XC2VM3654 (AMD Versal Prime Gen 2), A5D 051 (Altera Agilex 5 D-Series).
Which software is used to design with the XCZU65DR?
Designs for the XCZU65DR are built with AMD Vivado.
Other Zynq UltraScale+ RFSoC devices
| Device | LUTs | Vendor logic | DSP | Block RAM | Max I/O | Transceivers | PCIe | CoreScore |
|---|---|---|---|---|---|---|---|---|
| XCZU64DR | 150,000 LUT6 | 328K SLC | 1,872 | 15.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU63DR | 180,000 LUT6 | 393K SLC | 1,200 | 17.6 Mb | 154 | 4 GTY 28.21 Gb/s | — | — |
| XCZU42DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 152 | 8 GTY 28.21 Gb/s | — | — |
| XCZU65DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU67DR | 224,000 LUT6 | 489K SLC | 1,872 | 22.8 Mb | 154 | 8 GTY 28.21 Gb/s | — | — |
| XCZU25DR | 310,000 LUT6 | 678K SLC | 3,145 | 27.8 Mb | 347 | 8 GTY 28.21 Gb/s | Gen3 | — |
| XCZU21DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 280 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU27DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU28DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU29DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU39DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen3 | — |
| XCZU43DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU46DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 360 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU47DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU48DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 347 | 16 GTY 28.21 Gb/s | Gen4 | — |
| XCZU49DR | 425,000 LUT6 | 930K SLC | 4,272 | 38 Mb | 408 | 16 GTY 28.21 Gb/s | Gen4 | — |
Source: AMD Zynq UltraScale+ RFSoC Product Selection Guide, XMP105 (v1.12.1). Data is extracted automatically from the vendor's selection guide; verify critical values in the device data sheet.